Adaptive Address Translation Method and Controller for High Bandwidth and Low Voltage Systems

Abstract

The invention discloses an adaptive address conversion method and controller applied to a high-bandwidth low-voltage system. The adaptive address conversion method comprises the following steps of: receiving a plurality of request commands, wherein a memory address corresponding to each request command comprises a library address; converting memory addresses corresponding to the request commands to make library addresses corresponding to at least a part of every two adjacent request commands different; and converting the memory addresses corresponding to the request commands by performing numeric conversion to reduce the change digits of the memory addresses corresponding to every two adjacent request commands.

Description

technical field [0001] The present invention relates to an adaptive memory address translation method and a memory controller, and in particular to an adaptive memory address translation method and a memory controller applied to high-bandwidth and low-voltage systems. Background technique [0002] When the memory is reading / writing data, steps including activation, reading / writing commands, and pre-charging must be executed sequentially before data can be accessed. When the address of the memory is switched, whether the page address and the bank address are hit or not will affect the performance of the overall system. [0003] Please refer to figure 1 and figure 2 , figure 1 A schematic diagram showing an example of memory access, figure 2 draw figure 1 The timing diagram of the access instruction. At figure 1 In this case, if it is desired to access the data of the bank address C and the page address D first, and then access the data of the bank address E and the p...

AI Technical Summary

Problems solved by technology

Because the memory must first precharge the page address A in the bank address A, and then reactivate the next page address B to be accessed, the activation steps are as follows Figure 4 The shown cannot be hidden through the pipeline, reducing system performance

[0005] Therefore, the arrangement of the memory address is related to whether the overall system can effectively access the memory, thereby affecting the performance of the overall system

[0006] In addition, since the memory receives the memory address in the form of a single-ended signal, when the continuous memory address received by the memory needs to be carried, most of the bits will change at the same time, causing a large amount of instantaneous changes in the current, which in turn affects the electrical characteristics, making the logic Slower transitions between 1 and logic 0, causing the memory to sample the wrong memory address and not function properly at higher operating speeds

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