Optimization method of compiler of multi-issue embedded processor
A technology of embedded processor and optimization method, which is applied in electrical digital data processing, instruments, memory systems, etc., to achieve the effect of improving pipeline performance and solving compilation and optimization problems
Active Publication Date: 2015-01-28
天津国芯科技有限公司
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[0006] The purpose of the present invention is to provide a method for optimizing a multi-launch embedded processor compiler, to solve the problem of compiling and optimizing the multi-launch processor, and to improve the pipeline performance of the multi-launch processor
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[0026] like figure 1 As shown, the present invention is a multi-issue embedded processor compiler optimization method, which is based on the compiler front-end output as an intermediate expression in the form of a static single assignment tree (SSA Tree).
[0027] The intermediate expression in the form of an assignment tree generated by the front end of the compiler is converted into an instruction sequence according to the instruction template file, and the registers in the instruction sequence are virtual registers.
[0028] The specific form of the output command sequence, for example figure 2 As shown, there is no instruction set corresponding to a certain processor.
[0029] Among them: "ld" means fetching data from memory; "add" means addition operation; "mul" means multiplication operation; "bl" means jump operation with link register.
[0030] According to the characteristics of the processor pipeline, adjust the order of the instruction sequence, adjust the order ...
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The invention provides an optimization method of a compiler of a multi-issue embedded processor. The method comprises steps of (1) converting intermediate expression, namely converting the intermediate expression of an assignment tree form to an instruction sequence of a target instruction; (2) optimizing the instruction sequence, namely under the guidance of a multi-issue engine, adjusting the instructionorder of the instruction sequence obtainedin step (1) to obtain several instruction sequences with optimized instruction orders; (3) taking the several instruction sequences with optimized instruction orders obtained in step (2) as an individual and replacing a virtual register in the individual with a physical register to obtainan assembly code; (4) calculating an adaptation value, determining the best individual, and using the best individual as the individual of the next generation to carry out intersection and variation; and (5) repeating step (3) and step (4). The method provided by the invention has the advantages of solving of compiling optimization problems of the multi-issue processor, and improvement of the pipeline performance of the multi-issue processor.
Description
technical field [0001] The invention relates to a compilation optimization method of an embedded processor compiler, more precisely, an optimization method of an embedded processor compiler based on a multi-launch architecture. Background technique [0002] With the gradual increase in the performance requirements of modern embedded applications, multi-issue processors have been widely used in consumer electronics, network communications, aerospace, and complex industrial control. A multi-issue processor, simply put, is a processor that can execute multiple instructions simultaneously in one cycle. Currently relatively high-end embedded processors such as ARM's Cortex-A15, Cortex-A9, Cortex-A8, PowerPC's PPC470, and PPC460 are all multi-launch processors. These processors occupy most of the market in embedded high-end applications. [0003] Although the processor hardware supports multi-issue, and the hardware can adjust the order of instruction issuance, it generally only...
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IPC IPC(8): G06F9/45G06F9/38
Inventor 王勇王忠海肖佐楠郑茳
Owner 天津国芯科技有限公司