Delay adjustment method and data converter

Abstract

Disclosed are a delay adjustment method and data converter; the delay adjustment method comprises: the delay adjustment unit of a data converter receives a fixed clock; the delay adjustment unit of the data converter adjusts the fixed clock using a first adjustment amount to obtain a sampling clock, and adjusts the fixed clock using a second adjustment amount to obtain a clock for digital processing; the delay adjustment unit sends the sampling clock to the converter core of the data converter, and sends the clock for digital processing to a digital clock unit of the data converter. The present invention can realize delay adjustments within the data converter, thus reducing the design complexity and cost of the clock.

Description

technical field [0001] The invention relates to communication technology, in particular to a delay adjustment method and a data converter. Background technique [0002] In the digital pre-distortion (Digital Pre-Distortion, DPD for short) linearization technology, delay adjustment is one of the key technologies of DPD. The function of delay adjustment is to align downlink data and feedback data, and the alignment of downlink data and feedback data is an important prerequisite for various DPD operations. [0003] Since it is difficult to achieve flexible delay adjustment in the power amplifier, radio frequency channel and filter part, the existing delay adjustment technology generally adjusts the data converter, such as: Analog to Digital Converter (Analog to Digital Converter; hereinafter referred to as: ADC ) or a digital-to-analog converter (Digital to Analog Converter; hereinafter referred to as: DAC), the time delay is implemented. [0004] Specifically, the clock sent...

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Problems solved by technology

[0007] However, for the data converter of the Serdes interface, the working clock of the Serdes part cannot be adjusted during normal operation, and it must be kept stable, otherwise the Serdes interface will be disconnected, causing service interruption, for example: call drop

Therefore, in order to achieve the purpose of adjusting the delay of the data converter without affecting the normal operation of the Serdes interface, the external clock unit needs to provide two clocks, adjustable and non-adjustable, to the data converter at the same time. In this way, the external clock unit realizes the Serdes interface The delay adjustment function of the data converter will cause the design of the external clock unit to be more complicated, and the implementation cost will be greatly increased

[0008] To sum up, in the prior art, the delay adjustment function of the data converter is implemented in the external clock unit, which will cause the design of the external clock unit to be more complicated and the implementation cost to be high

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