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Data processing method and device

A data processing and data technology, applied in the field of data communication, can solve the problems of large design area, occupation, consumption, etc.

Active Publication Date: 2014-04-09
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This will consume quite a lot of Block RAM resources and occupy a large design area, especially when the number of channels Y is also large.
Even if ASIC is used to implement related logic circuits, such a large bit-width FIFO will bring pressure on layout and timing delay to the backend, and it will also occupy a large design area

Method used

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Embodiment Construction

[0060] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0061] image 3 It is a flow chart of the data processing method in the uplink direction of the embodiment of the present invention, such as image 3 As shown, the method of the present embodiment includes:

[0062] Step 101, in the uplink direction, after receiving the data input from the data bus, write the data input from the data bus into the uplink shared buffer according to the whereabouts indication of the data and the data valid bit field indication;

[0063] When the data is input by the data bus, it gives the whereabouts indication and valid bit segment indication...

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Abstract

The invention provides a data processing method and device. The method includes: writing the received data input by a data bus an uplink side sharing cache according to the heading direction indication and data significance bit field indication of the data; polling the uplink side sharing cache according to fixed time slot sequence to read the data in the uplink side sharing cache, and outputting the data to each corresponding channel. The method has the advantages that cache resources can be saved effectively while reliable data caching and bit width conversion are achieved, area and time sequence pressure can be lowered, and cache utilization rate can be increased.

Description

technical field [0001] The invention relates to the field of data communication, in particular to a data processing method and device. Background technique [0002] In the large-scale digital logic design in the field of data communication, sometimes in order to improve the processing capability of the logic circuit or to match the bit width of the bus on both sides of the logic circuit, it is necessary to convert the bit width of the data path of the logic circuit. Considering that the total bandwidth on both sides of the logic circuit may not necessarily be equal, or that one side may be congested, the logic circuit also needs to be able to buffer the data to be transmitted. [0003] for example figure 1 Such an application scenario is shown. On the uplink side, data is input from the data bus on one side and transmitted to Y channels (Y is an integer greater than or equal to 1) on the other side. On the downlink side, data is aggregated from Y channels according to the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/167G06F12/08G06F12/084
CPCG06F12/08G06F12/084G06F2212/1021G06F2212/281
Inventor 石欣琢
Owner SANECHIPS TECH CO LTD
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