3results about How to "Save cache resources" patented technology

The application discloses a log processing method and device, electronic equipment and medium, and belongs to the technical field of data processing. The log processing method comprises the following steps: acquiring N first parameter values in the case of running a target application; each first parameter value is used for indicating the occupation amount of a system resource of the electronic equipment by the target application, and N is a positive integer; in the case that a target parameter value in the N first parameter values is greater than or equal to a target threshold value, a target log switch is started, and log information is captured.

The application relates to an interrupt or exception event processing method, a processor and an electronic device. The method comprises the following steps: after an interrupt or exception event is detected by a write-back unit, flushing a pipeline and triggering a hardware stack operation; based on the stack operation, a microinstruction splitting unit splits a stack microinstruction sequence of the hardware stack to obtain a register stack switching instruction while a fetch unit sequentially obtains to-be-processed instructions; the microinstruction splitting unit switches a first register stack currently used to a second register stack based on the register stack switching instruction; and sends to-be-executed instructions to an execution unit; the execution unit executes the to-be-executed instructions to perform interrupt or exception processing, and stores intermediate data and / or result data generated after execution to the second register stack. The first register stack and the second register stack are physically isolated in the processor, and a microinstruction splitting mechanism automatically triggered by hardware is combined, so that an interrupt or exception processing flow is significantly optimized.

The application discloses an ICS circuit based on address mapping and parallel merging and an implementation method thereof, belongs to the technical field of communication physical layer data processing circuits, and aims at the defects of large storage overhead, high processing delay, insufficient multi-period row-by-row merging throughput, large LFSR bit-by-bit iterative scrambling start delay and low overall efficiency caused by the fact that a traditional ICS circuit relies on a physical interleaving matrix, and designs a three-stage cascaded ICS integrated high-speed processing architecture, including an interleaving processing module, a merging processing module, a scrambling processing module and corresponding implementation methods, relies on a full-link parallel pipeline design, realizes three-way bit stream interleaving, merging and scrambling integrated high-speed processing, solves the problems of large storage redundancy, high time delay, limited throughput and easy data blocking of the traditional circuit, has the characteristics of low time delay, small area, high throughput, stable operation and strong versatility, and can be widely adapted to wireless communication physical layer high-speed data real-time preprocessing scenes.