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Equal-delay distributed cache Ethernet MAC architecture

A distributed cache, Ethernet technology, applied in the field of communication, can solve the problem that the packet scheduling delay is difficult to keep consistent, and achieve the effect of achieving certainty and consistency, low jitter, and saving cache resources.

Pending Publication Date: 2022-05-13
芯河半导体科技(无锡)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Its scheduling effect is as follows figure 2 As shown, the scheduling in a packet may include two parts, the non-uniform scheduling area and the uniform scheduling area. Since the data is "pushed" into the cache with a certain acceleration ratio and piled up there for scheduling, it is difficult to maintain the scheduling delay of each packet. unanimous

Method used

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  • Equal-delay distributed cache Ethernet MAC architecture
  • Equal-delay distributed cache Ethernet MAC architecture
  • Equal-delay distributed cache Ethernet MAC architecture

Examples

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Embodiment 1

[0055] A schematic diagram of an equal-delay distributed cache Ethernet MAC architecture is shown in Image 6 shown. The specific implementation steps are as follows:

[0056] Step 1: If Image 6 As shown, user input data enters VOQ (Virtual OutputQueue, virtual output queue) through the multi-port shared bus;

[0057] The VOQ cache here only needs to absorb the flow of the upper link (marked as VOQ_Space0), and does not need to centrally set the cache part (marked as VOQ_Space1) that is exclusive to the sub-queue in the conventional VOQ to ensure continuous data flow. The VOQ outlet demultiplexes data based on the port. Each port supports two priority queues, e and p. The e queue has a high priority and can interrupt the transmission of the p queue to ensure that this queue is sent first. The final realization of the Layer 2 service adaptation logic scheduling effect is as follows: Figure 4 As shown, it is characterized by uniform intra-packet scheduling and controllable...

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Abstract

The invention relates to the technical field of communication, in particular to an equal-delay distributed cache Ethernet MAC (Media Access Control) architecture, which comprises the following steps of: based on a distributed cache thought, disassembling a cache part which is used for ensuring that a link is not cut off when back pressure is revoked in a traditional adaptive VOQ (Voice Over Quality) cache, and integrating the cache part into each existing downstream function sub-module; according to the method, point-by-point back pressure scheduling is combined, stepping scheduling of each register is achieved, and low delay and low jitter required by application scenarios such as a TSN network are achieved in cooperation with a modularized BR preemptive sub-module capable of being added and deleted, so that the certainty and consistency of scheduling delay are achieved.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to an equal-delay distributed cache Ethernet MAC architecture. Background technique [0002] Traditional Ethernet technology focuses on solving physical media conflicts, ensuring port bandwidth, and providing users with high-quality services, which greatly facilitates the development of communications, IT and other industries; however, with the continuous development of technology, in many emerging application scenarios, Such as industrial Ethernet, Internet of Things, intelligent driving, TSN (Time Sensitive Network, time-sensitive network), etc., the deficiency of traditional Ethernet transmission delay uncertainty is becoming more and more prominent. Designing an Ethernet with a high degree of transmission determinism, so as to achieve precise control of the target device, has become a problem that must be solved at present. [0003] Ethernet MAC (Media Access Control, med...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L67/1097H04L67/568H04L47/50H04L61/00H04L101/622
CPCH04L67/1097H04L47/50
Inventor 唐旭
Owner 芯河半导体科技(无锡)有限公司
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