NVMe submission queue control device and method

Abstract

The invention discloses an NVMe submission queue control device and method, and the device comprises: a submission queue command state detection circuit which is used for detecting whether the current state of each submission queue is non-empty or not; the first-level shared cache management circuit that is used for distributing corresponding first-level cache units in the same first-level shared cache for different submission arrays of which the current states are non-empty; and the submission alignment command acquisition circuit that is used for sending a submission alignment command acquisition request to the host end, so that the NVMe controller writes a submission queue command returned by the host end into the corresponding first-level cache unit. In this way, the utilization rate of the submission queue cache can be increased, cache resources can be saved, and the difficulty of hardware circuit layout and wiring of the submission queue cache is reduced.

Description

technical field [0001] The present application relates to the field of storage technologies, in particular to an NVMe submission queue control device and method. Background technique [0002] With the rapid development of cloud computing, artificial intelligence and the Internet of Things, terminal products and servers have an increasing demand for storage. In the process, NVMe (Non-Volatile Memory express,) SSD (Solid State Disk, solid state Hard disk) has also gained more and more attention in the field of storage technology due to its low latency, low power consumption, high bandwidth and many other advantages, and has also become a new trend in the development of storage devices. [0003] In the prior art, different SQs (i.e. Submission Queue, submission queue) of NVMe have different SQ SRAM (i.e. Static Random-Access Memory, static random access memory) cache resources, which to a certain extent, especially when NVMe supports When the number of SQs is large, SQ SRAM re...

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Problems solved by technology

[0003] In the prior art, different SQs (i.e. Submission Queue, submission queue) of NVMe have different SQ SRAM (i.e. Static Random-Access Memory, static random access memory) cache resources, which to a certain extent, especially when NVMe supports When the number of SQs is large, the SQ SRAM resources are wasted and the chip area is increased. At the same time, a large number of SQ SRAMs increases the difficulty of layout and wiring of the back-end hardware circuit, and the timing convergence is difficult.

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