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A pulse generator based on fpga fault detection

A pulse generator and fault detection technology, which is applied to the automatic control of power, electrical components, etc., can solve the problems of lack of versatility, unsupported detection trigger input step size, long detection time, etc.

Active Publication Date: 2018-07-20
BEIJING ZHONGCHUANGWEI NANJING QUANTUM COMM TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] For above-mentioned prior art, the object of the present invention is to provide a kind of pulse generator based on FPGA fault detection, and it is aimed at solving in existing FPGA fault detection, detection frequency is limited, resets trigger frequently, does not support detection trigger Input step size, occupying FPGA counter, long detection time and lack of versatility and other technical problems

Method used

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  • A pulse generator based on fpga fault detection
  • A pulse generator based on fpga fault detection
  • A pulse generator based on fpga fault detection

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Experimental program
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Embodiment 1

[0026] Figure 6 It is a schematic diagram of the actual detection of the pulse generator of the present invention. According to the characteristics of different FPGA time-critical components (used to generate or limit clock signals), set the number of compensation pulses based on the measured FPGA and the delay base of the first programming delay unit 2a △ 0. Cooperate with the pre-laid simple circuit for fault detection in the FPGA to form a phase-locked loop circuit PLL and a delay-locked loop circuit DLL. Compensate the working state of the counting unit 1a and the programming counting unit 1b, and the synchronization of the pulse start signal is guaranteed by the external level-controllable START terminal. Specifically, the pulse generator is in the working state. After the initial pulse is sent out, it receives the pulse reply from the FPGA through SCLK. After the pulses of different modes pass through the compensation loop and the programming loop respectively, they ...

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Abstract

The invention discloses a pulse generator based on FPGA fault detection, and relates to the field of integrated circuits. The technical problems of limited detection frequency, frequent trigger reset, unable trigger input step detection, FPGA counter occupancy, long detection time and being non-universal of the existing FPGA fault detection are solved. According to the invention, the circuit structure comprises clock input SCLK; clock input SCLK is connected with a compensation pulse counting unit; the output end of the compensation pulse counting unit is connected with a first programming delay unit; clock input SCLK is connected with a programming pulse counting unit; and the output end of the programming pulse counting unit is connected with a second programming delay unit. The pulse generator provided by the invention is used for FPGA fault detection.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a pulse generator based on FPGA fault detection. Background technique [0002] When the integration process goes below ultra-deep sub-micron, the traditional fault detection model is no longer applicable. There are two common test modes: full speed functional test and chain scan test. Full-speed functional test, generally used for non-programmable components or programmed components; the main method is to let the tested integrated components run at the highest clock frequency, but, because the highest frequency design is independent of the user terminal design, when running the test, the user terminal cannot Know the highest clock frequency of the integrated component. Chain-sweep testing, establishing a locked loop, by emitting, delaying, and capturing pulses, the delay of the matching path at the output is significantly different, ie a loop fault is detected. [0003] The ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/085
Inventor 汪海李国
Owner BEIJING ZHONGCHUANGWEI NANJING QUANTUM COMM TECH CO LTD