A single-event-hardened power-on-reset circuit suitable for SRAM-type FPGAs used in aerospace

Abstract

The invention discloses a single-particle reinforced power-on reset circuit applicable to an SRAM type FPGA for aerospace. The power-on reset circuit comprises a power supply VCC, three same power-on redundant modules, an error detection and redundant output control module and three controllable output buffers, wherein the error detection and redundant output control module can detect the power-on redundant modules with errors, and resets the power-on redundant modules for eliminating the accumulation of single event effects; and the error detection and redundant output control module can control the controllable output buffers to cut off the outputs of the power-on redundant modules with errors, and ensures the correct output of the power-on reset circuit. The power-on reset circuit eliminates the error accumulation phenomenon caused by single event upset effects, and meanwhile controls the outputs of the modules to eliminate the influence of the single event effects on the outputs, thus the remarkable capability of resisting the single event effects is achieved.

Description

technical field [0001] The invention relates to a single-event reinforced power-on reset circuit suitable for SRAM type FPGA used in aerospace, and belongs to the field of anti-single-event effect reinforced integrated circuits. Background technique [0002] The SRAM type FPGA chip needs a power-on reset process when starting. The power-on reset circuit gives a reset signal when the FPGA chip is started, and keeps a valid level. After the power supply voltage rises to a level where other circuits can work normally, the reset signal is changed, and other circuits on the chip are started. After success, maintain a stable state and make the chip work normally. When the existing power-on reset circuit is used in SRAM FPGA for aerospace, it will face serious reliability problems: the power-on reset circuit will generate single event upset (SEU) and single event transient (SET) in the harsh environment of space. single event effects. When single event upset (SEU) and single eve...

AI Technical Summary

Problems solved by technology

When the existing power-on reset circuit is used in SRAM FPGA for aerospace, it will face serious reliability problems: the power-on reset circuit will generate single event upset (SEU) and single event transient (SET) in the harsh environment of space. single event effect

When single event upset (SEU) and single event transient (SET) occur in the power-on reset circuit, a wrong power-on reset signal will be generated, resulting in power-off of the chip and loss of user functions, seriously affecting the reliability of aerospace SRAM FPGAs , with the advancement of technology, the sensitivity of SRAM-type FPGA chips to single event effects continues to increase, and higher requirements are placed on the reliability of power-on reset circuits.

At the same time, the reinforced SRAM FPGA for aerospace contains a variety of storage units. These storage units adopt different reinforcement measures due to different radiation resistance requirements, resulting in different voltages and different clearing times for these storage units to work normally. , the existing power-on reset circuit is difficult to guarantee a reasonable reset pulse width, especially as the process size shrinks, the deviation of different types of memory cells continues to increase, and higher requirements are placed on the correctness of the reset pulse width

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