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Structure applied to purley platform and supporting PCIE IOBOX

A platform and MOS tube technology, applied in the server field, can solve problems that affect CPU processing efficiency and increase processing burden

Inactive Publication Date: 2017-06-13
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This function is to virtualize the inside of the CPU into multiple hosts, so that multiple virtual machines can access the same PCIE device at the same time, but this is not a multi-host shared IO on the hardware, but based on the processor having multiple cores. , this method increases the processing load of the CPU and affects the processing efficiency of the CPU

Method used

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  • Structure applied to purley platform and supporting PCIE IOBOX

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Embodiment Construction

[0021] In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the specific embodiments. Obviously, the implementation described below Examples are only some embodiments of the present invention, but not all embodiments. Based on the embodiments in this patent, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of this patent.

[0022] The present invention provides a structure applied to the purley platform to support PCIE IOBOX, such as figure 1 As shown, it includes: backplane 2, PCIE Switch module 1, first power chip 3, second power chip 4, first X16PCIE slot 5, second X16PCIE slot 6, third X16PCIE slot 7, fourth X16PCIE slot 7 Slot 8, the first P3V3_STBY terminal 13, the second P3V3_STBY te...

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Abstract

The invention provides a structure applied to a purley platform and supporting a PCIE IOBOX. The structure comprises a backboard, a PCIE Switch module, a first X16PCIE slot, a second X16PCIE slot, a third X16PCIE slot, a fourth X16PCIE slot, a first P3V3_STBY wiring terminal, a second P3V3_STBY wiring terminal, a first P12V_STBY wiring terminal, a second P12V_STBY wiring terminal, a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and an eighth MOS tube. The purposes of plugging multiple CPU in the first X16PCIE slot, the second X16PCIE slot, the third X16PCIE slot and the fourth X16PCIE slot and sharing the same PCIE resource are achieved.

Description

technical field [0001] The invention relates to the field of servers, in particular to a structure applied to a purley platform to support PCIE IOBOX. Background technique [0002] In the design of high-end servers on the new platform, in order to fully utilize the hardware resources of PCIE devices, reduce the idle rate of hardware, and increase the performance of system hardware, it is an effective design method that multiple CPUs can share a PCIE device. This implementation not only requires the PCIE device to support the functions of multiple VFs (Virtual Functions), but also adds a PCIE Switch to the IOBOX so that it can be addressed according to the BUS number of each PCIE device. [0003] In the current IOBOX design, the CPU directly outputs the PCIE resources to the SLOT, and then connects the IO devices. Such a design can only support the SR-IOV (Single-Root I / O Virtualization) function defined by the PCIE specification. This function is to virtualize the inside o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40
CPCG06F13/4068G06F13/4022G06F2213/0024
Inventor 刘东洋张燕群
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD