Memory and its method of operation

Abstract

The invention discloses a memory. The memory unit adopts the structure of three gate structures and two source-drain regions. The same row in the array structure includes two control lines and one word line, which are respectively connected to the corresponding control gates of the memory units. and the selection gate, the memory cells in the same column are connected in series, the memory cells in the same column are connected to two bit lines, the first source and drain regions of each memory cell in odd rows and the second source and drain regions of each memory cell in even rows are all connected to the first bit line, the second source and drain regions of each memory cell in odd rows and the first source and drain regions of each memory cell in even rows are all connected to the second bit line, the memory cell structure and The array structure can realize the reasoning operation, and the input signal of the reasoning operation adopts the input current of the word line in each row and the output signal adopts the output voltage of the bit line corresponding to each column. The invention also discloses the operation method of the memory. The invention can realize the integrated operation of storage and calculation.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a memory. The invention also relates to a method for operating the memory. Background technique [0002] like figure 1 Shown is a structural diagram of a storage unit (Cell) of an existing memory; each storage unit 1 includes: a first gate structure 104, a second gate structure 105, a third gate structure 106, a first source-drain region 102 and the second source and drain region 103 . [0003] The first gate structure 104 is composed of a first gate dielectric layer 107 formed on the surface of the semiconductor substrate 101 , a floating gate (Floating Gate, FG) 108 , a second gate dielectric layer 109 and a polysilicon control gate 110 . The first source-drain region 102 and the second source-drain region 103 are generally N+ doped, and the semiconductor substrate 101 is a P-type doped silicon substrate. [0004] The second gate structure 105 is composed of...

AI Technical Summary

Problems solved by technology

Existing memories cannot realize single-storage-bit operations, thus making it impossible to realize storage-computing integration

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