Memory and method for operating same

Abstract

The invention discloses a memory. A memory cell uses three gates and two source / drain regions. The same row in an array structure includes two control lines and one word line which are connected to the corresponding control gate and the selection gate of the memory cell respectively. The memory cells in the same column are connected in series, and are connected with two bit lines. The first source / drain region of each memory cell in the odd rows and the second source / drain region of each memory cell in the even rows are connected to the first bit line. The second source / drain region of each memory cell in the odd rows and the first source / drain region of each memory cell in the even row are connected to the second bit line. The memory cell structure and the array structure of the memory ofthe invention can implement an inference operation, and the input signal of the inference operation uses the input current of the word line in each row and the output signal of the inference operation uses the output voltage of the bit line corresponding to each column. The invention also discloses a method for operating the memory. The memory can realize a storage and calculation integrated operation.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a memory. The invention also relates to a method for operating the memory. Background technique [0002] Such as figure 1 Shown is a structural diagram of a storage unit (Cell) of an existing memory; each storage unit 1 includes: a first gate structure 104, a second gate structure 105, a third gate structure 106, a first source-drain region 102 and the second source and drain region 103 . [0003] The first gate structure 104 is composed of a first gate dielectric layer 107 formed on the surface of the semiconductor substrate 101 , a floating gate (Floating Gate, FG) 108 , a second gate dielectric layer 109 and a polysilicon control gate 110 . The first source-drain region 102 and the second source-drain region 103 are generally N+ doped, and the semiconductor substrate 101 is a P-type doped silicon substrate. [0004] The second gate structure 105 is composed...

AI Technical Summary

Problems solved by technology

Existing memories cannot realize single-storage-bit operations, thus making it impossible to realize storage-computing integration

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