A high speed spi master mode controller

Abstract

Aiming at the deficiencies in the prior art, the present invention relates to a high-speed SPI master mode controller. Through structural improvements, the SPI controller works in the low-frequency clock domain and can still improve the operating frequency of the SPI interface, so as to achieve the support of the SPI Flash device itself. The limit of speed. In order to achieve the above object, the present invention is realized through the following technical solutions: a high-speed SPI master mode controller, the clock signal is provided by the PLL, and the whole controller is divided into: a slow clock domain and a high-speed clock domain, and the PLL passes through different clock divisions. The frequency converter provides two main clock signals, the slow clock signal is provided to the slow clock domain, and the high-speed source clock signal is provided to the high-speed clock domain. Through such a technical scheme, the present invention divides the functions of different clock domains through the asynchrony of the high-speed SPI controller; realizes the function of high-speed SPI Flash access, and saves reading and writing time. Especially in the application scenario of using SPI FlashBoot, the controller can greatly optimize the boot time.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, in particular to a high-speed SPI master mode controller. Background technique [0002] SPI (Serial Peripheral Interface), Serial Peripheral Interface, is a synchronous serial interface technology introduced by Motorola. SPI is mainly used between EEPROM, Flash, real-time clock (RTC), digital-to-analog converter (ADC), digital signal processor (DSP) and digital signal decoder. Generally, the maximum clock frequency of the SPI module is 1 / 2 of the system clock frequency. Although the transmission rate of SPI is mainly limited by the ability of the CPU to process SPI data, when communicating with another very high-speed SPI device, the maximum clock frequency of SPI may restrict its transmission rate. The higher the clock, the faster the reading and writing speed can be supported. However, when the SPI clock frequency increases, its controller also needs to work at a higher clock fre...

AI Technical Summary

Problems solved by technology

[0004] Such a solution mainly starts with the transmitted data, and improves the efficiency of data transmission through data optimization, but the transmission rate of the SPI interface itself, especially the transmission rate of the low-frequency clock domain, has not been significantly improved.

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