6 results about "Synchronous Serial Interface" patented technology

The present invention relates to a slave device that implements a synchronous serial interface using a dual serial peripheral interface. The slave device includes an MCU and an external interface provided on the MCU. The external interface includes two serial peripheral interfaces SPI, namely a first serial peripheral interface SPI1 and a second serial peripheral interface SPI2. The first serial peripheral interface SPI1 includes a first data output interface SPI1MISO, a first data input interface SPI1MOSI, and a first clock input interface SPI1Clock. The second serial peripheral interface SPI2 includes a frame synchronization signal input interface SPI2CS and a second clock input interface SPI2Clock. The first clock input interface SPI1Clock and the second clock input interface SPI2Clock are connected. Compared with the prior art, the present invention has the advantages of greatly reducing development costs and transplantation costs.

The disclosure provides a multi-channel synchronous serial interface parallel communication system and a data transmission method, which can be applied to the technical field of data communication. The system comprises a substrate; a master chip located in the middle part of the substrate, used for data transceiving and protocol analysis; at least three groups of synchronous serial interface channels located on the second side of the substrate, each group of the synchronous serial interface channels comprising two differential transceivers; a host computer interaction unit located on the first side of the substrate and a power supply circuit comprising a two-stage voltage reduction structure, the host computer interaction unit integrating multiple serial interfaces to adapt to different host computers. The method comprises: receiving and verifying a host computer data request frame, storing valid data into an independent cache area of a corresponding channel and returning a response; synchronously listening to clock signals of each channel, and driving corresponding data differential transceivers to output cached data under the falling edge of each clock. The disclosure realizes hardware-level parallel, synchronization and low-delay transmission of multi-channel data.

The application relates to a host device using a serial peripheral interface to replace a synchronous serial interface, the host device comprising two serial peripheral interfaces SPI, namely a first SPI1 and a second SPI2, the first SPI1 comprising a first data output interface SPI1MISO, a first data input interface SPI1MOSI and a first clock signal SPI1Clock, the second SPI2 comprising a second frame synchronization signal output interface SPI2MOSI and a second clock signal SPI2Clock, and the first clock signal SPI1Clock being connected with the second clock signal SPI2Clock. Compared with the prior art, the application has the advantages of realizing the same effect as SSI communication by only adding one interface.

The invention discloses a multi-source data recording device, and the device comprises a power management module which is provided with a power state detection unit and a backup energy maintaining unit; the multi-protocol input interface module at least comprises a synchronous serial interface and a network interface; the nonvolatile storage module is provided with a bad block management mechanism; the processing core is configured to generate a self-check report containing an incremental session identifier and a current storage offset during power-on initialization; establishing a state monitoring channel to output a self-check report and an internal resource state; when abnormal power failure is detected, a backup energy maintaining unit is utilized to ensure that an ongoing data storage transaction is completed, and a mapping relation between logic addresses and physical addresses of all to-be-submitted data is solidified and stored; and after power-on again, reading the mapping relation to recover the data record. According to the method, the integration of power supply exception processing and data recording is realized, the recording session identifier is ensured to be continuously increased under the condition of transient interruption of an extreme power supply, and the recovery of a cross-multi-data-stream record is realized.

This invention provides a method and system for receiving SSI protocol data based on SPI, belonging to the field of data transmission. The method includes: configuring a microcontroller to enable its serial peripheral interface to perform data transmission using direct memory access; determining the target number of bytes based on the data acknowledgment response time length of the synchronous serial interface, the total number of effective bytes, and the baud rate of the serial peripheral interface, and determining a synchronization clock signal and data to be transmitted based on the target number of bytes; sending the synchronization clock signal and data to be transmitted to the synchronous serial interface through the serial peripheral interface, while simultaneously receiving data to be decoded sent by the synchronous serial interface, and storing the data to be decoded in a receive buffer; decoding the data to be decoded in the receive buffer when the number of bytes of data to be decoded in the receive buffer equals the target number of bytes. This invention allows the microcontroller to directly receive SSI protocol data, reducing hardware complexity and cost.

The invention discloses a radar system based on a high-speed synchronous serial interface and a communication method and device, and the system comprises a transmitting end and a plurality of subsystems corresponding to the transmitting end, and the transmitting end is in communication connection with each subsystem through the high-speed synchronous serial interface and a timing signal interface; the sending end comprises a central interface and a timing subsystem; the central interface receives commands and data sent by the display control system, and the timing subsystem generates radar timing synchronization pulses; the communication mode of the sending end and the subsystem is configured to enable signals, synchronous clock signals and serial data signals to transmit differential level signals in a three-wire synchronous serial mode; under the triggering of a radar timing synchronization pulse, a sending end simultaneously sends single-ended signals of enabling, a synchronous clock and serial data to a corresponding subsystem; and realizing time sequence synchronization in the radar system by adopting a running water time sequence mechanism of preprocessing in the current period and taking effect in the next period. According to the invention, high-speed and long-distance reliable communication is realized while the number of cables is reduced, and the hardware complexity and cost are greatly reduced.