Stacked chip, manufacturing method and electronic device

Abstract

The embodiment of the application provides a stacked chip, a manufacturing method and an electronic device, which can reduce the manufacturing cost of the stacked chip. The stacked chip includes: a carrier wafer having a first groove disposed therein; a first wafer arranged in the first groove; a second wafer stacked above the carrier wafer and the first wafer, the second wafer having a surface area larger than a surface area of the first wafer; and a redistribution layer located between the second wafer and the first wafer, wherein the second wafer is electrically connected with the first wafer through the redistribution layer. In the embodiment of the application, the first groove in the carrier wafer is used for providing support and stability for the first wafer, and the second wafer with a large area is stacked on the first wafer with a small area, so that the first wafers with small areas can be manufactured on the wafer as much as possible while a chip stacking structure is realized, the cost of the single first wafer is reduced, and the whole manufacturing cost is reduced.

Description

technical field [0001] The present application relates to the field of semiconductor chips, and more specifically, to a stacked chip, a manufacturing method, an image sensor and an electronic device. Background technique [0002] With the development of semiconductor and integrated circuit technology, the device types of chips are becoming more and more abundant, and the integration level is getting higher and higher. On the two-dimensional plane, with the development of semiconductor technology to a certain extreme level, it is impossible to further improve the performance of the chip. Therefore, a concept of three-dimensional stacking is currently proposed in the industry, which expands the chip from two-dimensional to three-dimensional, that is, chip modules with different functions are stacked up and down together for packaging, so as to improve the overall performance and yield of the chip. [0003] In one implementation, the upper wafer (Die) and the lower wafer are st...

AI Technical Summary

Problems solved by technology

In order to meet the stacking process requirements, the upper wafer and the lower wafer have the same wafer size, and the number of upper wafers on the upper wafer is equal to the number of wafers on the lower wafer, but when the upper wafer and the lower wafer are not the same type of wafer, This stacking method will cause waste of wafer area and increase the manufacturing cost of stacked chips

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