Broadband parallel channelized receiving method based on embedded GPU

A receiving method and channelized technology, applied in the field of broadband parallel channelized receiving based on embedded GPU, can solve the problems of high development cost, poor portability, inconvenience of portability, etc., and achieve low power consumption, good portability, and improved processing. The effect of efficiency

Active Publication Date: 2020-10-16
CHONGQING UNIV OF POSTS & TELECOMM
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Aiming at the current wideband digital channelized receivers are mostly realized by DSP and FPGA platforms, which have the disadvantages of poor portability, inconvenient portabil

Method used

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  • Broadband parallel channelized receiving method based on embedded GPU
  • Broadband parallel channelized receiving method based on embedded GPU
  • Broadband parallel channelized receiving method based on embedded GPU

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Experimental program
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Embodiment 1

[0050] The traditional digital channelization structure is based on the low-pass filter bank digital channelization structure, such as figure 2 , this structure divides the broadband signal x(n) into K signals, and each signal is first moved to the baseband through down-conversion processing, then low-pass filtering is performed through a low-pass filter, and finally the data is changed through the decimator. rate to finally obtain the signal. The digital channelization structure based on low-pass filter bank is expressed as:

[0051]

[0052] Among them, h LP (n) represents a low-pass filter.

[0053] Expand the above formula to get:

[0054]

[0055] like:

[0056] x p (m-i)=x(mD-iD-p),

[0057] h p (i)=h LP (iD+p)

[0058] can get:

[0059]

[0060] take further

[0061]

[0062] but

[0063]

[0064]

[0065] Substituting the above two equations into the digital channelization structure based on low-pass filter banks can obtain the mathematic...

Embodiment 2

[0073] Such as Figure 4 , in the OpenCL platform model, an OpenCL device contains multiple computing units, and each computing unit contains multiple processing elements. These processing elements are also called work items. OpenCL computing tasks are composed of these mutually independent processing elements. implement. According to different access permissions of threads, each processing element can access four storage spaces with different permissions: private memory, local storage area, constant memory and global memory. The way they are used in the program largely determines the performance of the program. , generally speaking, their size and access speed are different.

[0074] The index of the wideband digital channelized receiver designed in this embodiment is to divide the wideband signal with a bandwidth of 6.144MHz into 3KHz, and divide it into 2048 channels in total. Due to the large number of channels, if only a single-stage channelization process is used, a la...

Embodiment 3

[0084] In the polyphase DFT channelization structure, it is necessary to take the signal points on each channel and perform DFT to obtain the corresponding channelization processing results on the channel. In this paper, the fast Fourier transform (FFT) is used [7] to replace DFT processing to improve computational efficiency.

[0085] The input data of DFT is grouped by parity, and the FFT expression can be derived by using the reducibility and periodicity of the rotation factor, which is expressed as:

[0086]

[0087]

[0088] Among them, X 1 (k), X 2 (k) is the sequence obtained after parity grouping of the input sequence x(k) after N / 2 point DFT, is the rotation factor, and N is the signal point to be processed. Through decomposition, the calculation amount of DFT can be effectively reduced. Since N is a positive integer power of 2, The point DFT can continue to be decomposed until it is decomposed into a 2-point DFT. This operation is called a butterfly oper...

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Abstract

The invention relates to the technical field of communication, in particular to a broadband parallel channelized receiving method based on an embedded GPU, which comprises the following steps: constructing an OpenCL platform which comprises a work item and a work group; extracting broadband signals read into the OpenCL platform, wherein the extraction interval is the number of channels, originallyread-in one-dimensional data form a two-dimensional matrix after extraction, and the number of rows of the two-dimensional matrix is the number of channels; allocating each row of data to a work group for processing, wherein each work group multiplies the input data in the work group by a first factor; filtering the data on each channel and the multiphase filter coefficient on the branch; multiplying the filtered data by a second factor; and performing FFT operation on the formed two-dimensional matrix according to columns to obtain data output on each channel. According to the method, the computing tasks of multiple channels are processed at the same time, and the task processing efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a wideband parallel channelized receiving method based on an embedded GPU. Background technique [0002] In communication, in order to achieve parallel reception of multiple signals in broadband signals, researchers at home and abroad have proposed a variety of efficient digital channelization structures [1] , can channelize the broadband signal of the entire sampling bandwidth, and obtain multiple signals at the same time, so as to realize full probability reception. In order to realize an efficient digital channelization structure, at present, most researchers use DSP platform and FPGA to implement, but these two implementation methods are not portable, and the development cost is high. [0003] As the programmability of the GPU continues to increase, the application capabilities of the GPU have gone far beyond the graphics rendering task. The research on using the GPU t...

Claims

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Application Information

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IPC IPC(8): H04B1/06G06F8/30G06F8/76G06F17/16
CPCH04B1/06G06F8/76G06F8/30G06F17/16H04B1/16H04B1/001H03H17/0266H03H17/0273
Inventor 李国军田飞翔叶昌荣王遵立罗一平林金朝
Owner CHONGQING UNIV OF POSTS & TELECOMM
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