Double-stack three-dimensional memory and manufacturing method thereof

Abstract

The invention provides a double-stack three-dimensional memory and a manufacturing method thereof. The method comprises the steps: etching a first part, located in a core area, of a substrate downwards in the stacking direction, so that a height difference is formed between a second part, located in a stepped area, of the substrate and the first part; forming a lower stack on the first portion ofthe substrate and forming a stepped stack layer on the second portion of the substrate; forming an insulating connection layer on the lower stack and the stepped stack layer, wherein a height difference exists between a first part, located in the core area, of the insulating connection layer and a second part, located in the stepped area, of the insulating connection layer; and removing at least apart of the second part of the insulating connection layer from above in the stacking direction such that a height difference is reduced. In the formed double-stack three-dimensional memory, a firstpart, located in a core area, of a substrate is lower than a second part, located in a stepped area, of the substrate to form a step.

Description

technical field [0001] The present disclosure generally relates to the technical field of semiconductors, and in particular, to a dual-stack three-dimensional memory and a manufacturing method thereof. Background technique [0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage densities, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address density and performance limitations in planar memory cells. [0003] To further increase the storage capacity in 3D memories, the number of vertically stacked memory cells has been greatly increased while reducing the lateral size of the memory cells. As a result, the aspect ratio of 3D memory cells has increased significantly, introducing complexity in fabrication. For example, it is challenging to form the channel layer without damaging the memory layer on the sidewalls of t...

AI Technical Summary

Problems solved by technology

As a result, the aspect ratio of 3D memory cells has increased significantly, introducing complexity in fabrication

For example, it is challenging to form the channel layer without damaging the memory layer on the sidewall of the channel hole

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