Convolutional hardware accelerator based on RS (Reed-Solomon) data stream and method thereof

A technology of hardware accelerator and data flow, which is applied in the direction of reasoning method, electrical digital data processing, digital computer components, etc.

Pending Publication Date: 2022-01-21
NANJING UNIV
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  • Application Information

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Problems solved by technology

Although the convolutional neural network model can be deployed on a graphics processor GPU with a high degree of parallelism for training or reasoning, which can have a great speed advantag

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  • Convolutional hardware accelerator based on RS (Reed-Solomon) data stream and method thereof
  • Convolutional hardware accelerator based on RS (Reed-Solomon) data stream and method thereof
  • Convolutional hardware accelerator based on RS (Reed-Solomon) data stream and method thereof

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Embodiment Construction

[0034] The scheme of the present invention will be described in detail below in conjunction with the accompanying drawings,

[0035] Such as figure 1The structural block diagram of the convolution hardware accelerator based on RS row fixed data flow is shown, including the controller, DDR controller, on-chip data cache unit (RAM), off-chip DDR memory, data distribution module, photoelectric calculation module and result collection module. Off-chip DDR memory for storing raw image data and neural network inference result data. The on-chip data cache unit is used to store the original image data read from the off-chip DDR memory, convolution kernel weight data and convolution calculation intermediate results. The DDR controller is used to control the data interaction between the off-chip DDR memory and the on-chip data cache unit. The photoelectric computing module is used to complete the convolution operation of each layer of the network, including multiple photoelectric com...

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Abstract

The invention discloses a convolution hardware accelerator based on RS (Reed-Solomon) data stream and a method thereof. The accelerator comprises an off-chip DDR (Double Data Rate) memory; an on-chip cache module is used for storing the original image data, the convolution kernel weight data and the convolution calculation intermediate result read from the off-chip DDR memory; a DDR controller is used for controlling data interaction between the off-chip DDR memory and the on-chip cache module; a data distribution module is used for transmitting the required weight and excitation data to the photoelectric calculation module according to the current calculation configuration information and the calculation rule of the photoelectric calculation module; the photoelectric calculation module is used for completing convolution operation of each layer of network; and the result collection module is used for receiving the convolution results of the photoelectric calculation module and splicing the results to obtain the input of the next layer, or storing the splicing results in an off-chip DDR memory. According to the method, convolution operation is carried out based on an RS data stream mode, data reuse is maximized, access to off-chip DDR is reduced, and energy efficiency is improved.

Description

technical field [0001] The invention relates to a row-fixed (RS) data flow-based convolution hardware accelerator architecture and a method thereof, and belongs to the technical field of hardware accelerated neural networks. Background technique [0002] In recent years, with the development of computer science and Internet technology, the scale of world data has exploded, and artificial intelligence has also transformed from early artificial feature engineering to learning from large amounts of data. Inspired by brain neuroscience, the neural network model formed after many years of evolution has achieved great results in the field of machine learning, and has been widely used in computer vision, speech recognition, and natural language processing. [0003] In order to deal with complex problems or improve the accuracy of the model, the scale of the neural network model is getting larger and larger, resulting in the need for a large amount of computing resources. Large-sca...

Claims

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Application Information

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IPC IPC(8): G06N3/067G06N3/04G06N5/04G06F15/78
CPCG06N3/0675G06N5/04G06F15/781G06F15/7846G06N3/045Y02D10/00
Inventor 王宇宣李帅梅正宇潘红兵
Owner NANJING UNIV
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