A kind of manufacturing method of finfet

Abstract

The invention relates to the technical field of finfet, and discloses a method for manufacturing a finfet. In actual use, after the gate polysilicon layer is fabricated on the substrate and the surface of the substrate is cleaned with a cleaning solution, the gate polysilicon layer and the surface of the substrate are cleaned. The contact corner of Fin is etched to reduce the contact corner between the gate polysilicon layer and Fin, thereby preventing the contact corner between the gate polysilicon layer and Fin from being too large and causing the gate of the finished finfet to have too large a contact corner with Fin; and Or when the gate polysilicon layer on the substrate is removed, a filling layer is made on the gate polysilicon layer first, and then a high dielectric layer and gate metal are made to reduce the contact between the finfet gate and Fin Corner, thereby avoiding too large contact corner between the gate of finfet and Fin, which will affect the AC performance of finfet, and improve the yield rate of finfet.

Description

technical field [0001] The invention relates to the technical field of finfet, in particular to a manufacturing method of finfet. Background technique [0002] During the development of MOS tubes, the size of MOS tubes, that is, the channel length, is constantly shrinking. The reduction of the channel length shortens the transmission time of electrons between the drain and the source, the faster the switching speed of the transistor is, the clock frequency of the CPU is correspondingly increased, and the power consumption of a single transistor is also reduced. These are all conducive to the improvement of computer computing performance. In addition, the size of the transistor is reduced, and more transistors can be integrated on the same silicon chip area. The increase in the integration level means that the function of the chip will increase, and the cost will be further reduced. However, when the channel length of the planar MOS transistor is reduced to be comparable to...

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Problems solved by technology

However from figure 1 It can be found that the polysilicon gate at the gate position has corners when it is close to Fin, and the corners will become more serious as the size of Fin shrinks, which will affect the performance of finfet, such as reducing the AC performance of finfet, or directly causing nFETSiP missing. nFETSiP missing means that the source and drain regions of the finfet are grown in situ after phosphorus-doped silicon epitaxy. If the grown film cannot completely cover the polysilicon gate at the gate position, the cleaning solution will etch the source of the finfet during the subsequent SCI process. In-situ phosphorus-doped silicon epitaxy for electrode and drain region growth reduces the yield of finfet

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