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Semiconductor integrated circuit

一种集成电路、半导体的技术，应用在半导体集成电路领域，能够解决不可能精确估算电容、物理布线图不清楚等问题

Inactive Publication Date: 2006-02-01
FUJITSU SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, there are cases where the physical wiring diagram of the black box is unclear, so label any areas where the physical wiring diagram is clear to estimate the effect of crosstalk and the generation and capacitance between wiring
In this case, if there is a black box near the marked area when the estimation is made, it is extremely impossible to accurately estimate the effect of the black box on the crosstalk in the marked area and the resulting capacitance between the traces

Method used

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  • Semiconductor integrated circuit
  • Semiconductor integrated circuit
  • Semiconductor integrated circuit

Examples

Experimental program
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Embodiment Construction

[0034] An embodiment of the present invention will be described below with reference to the drawings. The shielding structure in this embodiment is a layout structure in which, if the internal area or the external area of ​​the macro device etc. Shield wiring is given on the layer. Figures 1 to 4 shows a specific embodiment of a plan layout structure, and Figure 5 An example of a longitudinal cross-sectional structure when wiring lines of these planar layout structures are stacked is shown.

[0035] figure 1 It is a top view showing a layout structure in which shield wiring is arranged on the border of a black box as a first embodiment. exist figure 1 In , the rectangular inner area indicated by the dotted line 1 is a black box composed of macro devices and the like 2 . The shield wiring 3 is given on the boundary of the black box 1 indicated by the dotted line so as to surround the inner area of ​​the black box 1 .

[0036]External terminals 4 electrically connected t...

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PUM

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Abstract

In a semiconductor integrated circuit a shield wiring (3) is provided on a boundary of a target region to be shielded of macros (2), an inner side of the boundary, an outer side of the boundary, or an inner side and an outer side of the boundary, each being as a black box (1), so as to surround the target region. This shield wiring (3) is electrically connected to a power supply terminal or a power supply wiring (4) of the macros or the like, or to a power supply wiring on another wiring layer through a contact section (5), thereby fixing a potential of the shield wiring. An accurate delay value is then obtained by estimating an influence of crosstalk between a wiring in a region where the physical wiring pattern is clear and the shield wiring and also estimating a capacitance produced between the wirings.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims the benefit of priority from Japanese Patent Application No. 2002-075483 filed on March 19, 2002, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to a semiconductor integrated circuit, and more particularly to a shield structure for a semiconductor integrated circuit in which a macro device (macro) such as a functional block or a hierarchical block given by a hierarchical layout (hereinafter referred to as a "macro device, etc.") is surrounded by a shielded wiring. "). Background technique [0004] In the design stage of a semiconductor integrated circuit, it is necessary to obtain delay values ​​of wiring and gates for delay simulation. For this reason, the influence of crosstalk and capacitance generated between wirings must be estimated from the wiring pitch. When the influence of crosstalk and the inf...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/82H01L27/00H01L23/52H01L21/3205H01L21/822H01L23/522H01L23/552H01L27/04
CPCH01L23/5225H01L2924/0002H01L23/552H01L2924/00H01L27/04
Inventor 江岛崇田岛正吾
Owner FUJITSU SEMICON LTD