Wafer structure and bumping manufacturing process
一种制造工艺、晶片的技术,应用在晶片结构以及凸块制造工艺领域,能够解决破裂、变形、损坏基板300电连接关系等问题,达到确保电连接关系的效果
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[0050] FIG. 3 is a schematic cross-sectional view of a wafer structure according to an embodiment of the invention. Please refer to FIG. 3 , the chip structure 400 mainly includes a semiconductor substrate 410 , a plurality of bonding pads 412 , a protection layer 420 , a plurality of elastic members 430 , a plurality of UBM layers 440 and a plurality of bumps 450 . The semiconductor substrate 410 has an active surface S1, and includes a plurality of semiconductor elements (not shown in the figure) and a plurality of bonding pads 412 disposed on the active surface S1. In an embodiment of the present invention, the semiconductor substrate 410 can be a silicon wafer, and the semiconductor elements on the active surface S1 can be manufactured by semiconductor manufacturing process, and are electrically connected to other chips or elements through the bonding pads 412 . The material of the pad 412 can be copper, aluminum or other conductive materials. The passivation layer 420 is...
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