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Wafer structure and bumping manufacturing process

一种制造工艺、晶片的技术,应用在晶片结构以及凸块制造工艺领域,能够解决破裂、变形、损坏基板300电连接关系等问题,达到确保电连接关系的效果

Inactive Publication Date: 2007-06-27
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if there is still water or solvent remaining in the polymer material 340a covered by the metal shell 340b after the manufacturing process of the soft bump 340 is completed, the soft bump may be caused when it is heated. 340 expansion, cracking or deformation, therefore, will damage the electrical connection relationship between the substrate 300 and other components

Method used

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  • Wafer structure and bumping manufacturing process
  • Wafer structure and bumping manufacturing process
  • Wafer structure and bumping manufacturing process

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Embodiment Construction

[0050] FIG. 3 is a schematic cross-sectional view of a wafer structure according to an embodiment of the invention. Please refer to FIG. 3 , the chip structure 400 mainly includes a semiconductor substrate 410 , a plurality of bonding pads 412 , a protection layer 420 , a plurality of elastic members 430 , a plurality of UBM layers 440 and a plurality of bumps 450 . The semiconductor substrate 410 has an active surface S1, and includes a plurality of semiconductor elements (not shown in the figure) and a plurality of bonding pads 412 disposed on the active surface S1. In an embodiment of the present invention, the semiconductor substrate 410 can be a silicon wafer, and the semiconductor elements on the active surface S1 can be manufactured by semiconductor manufacturing process, and are electrically connected to other chips or elements through the bonding pads 412 . The material of the pad 412 can be copper, aluminum or other conductive materials. The passivation layer 420 is...

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Abstract

A wafer structure including a semiconductor substrate, elastic elements, under bump metallurgic (UBM) layers and bumps is provided. The semiconductor substrate has an active surface, and it includes pads disposed on the active surface. The elastic elements are disposed on the pads respectively. Each elastic element has an opening, such that a portion of each pad is exposed from the opening of the corresponding elastic element. The UBM layers cover the elastic elements respectively, and each UBM layer is connected to the corresponding pad. The bumps are disposed on the UBM layers respectively.

Description

technical field [0001] The present invention relates to a wafer structure and a bump manufacturing process, and in particular to a wafer structure and a bump manufacturing process for releasing the pressure on the bump. Background technique [0002] In recent years, flat panel display elements having the advantages of high image display quality, high space efficiency, low power consumption, and no radiation have been widely used in medium-sized or small portable TVs, cell phones, camcorders, notebook computers, In desktop computers, projection TVs, and other computer products. Therefore, flat panel display devices have replaced the known cathode ray tube (CRT) and become the mainstream in the market. Generally speaking, after the manufacturing process of flat-panel display elements is completed, a chip on glass (COG) process is required, so that the flat-panel display elements can be electrically connected to external systems through some chips to provide power or driving s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/485H01L21/28H01L21/60
CPCH01L2924/01015H01L2924/0001H01L2924/01082H01L24/13H01L2924/01079G02F1/13452H01L2924/01033H01L2224/13144H01L2924/01029H01L2224/13099H01L2924/01078H01L2224/131H01L24/11H01L2924/01013H01L2924/014H01L24/05H01L2224/05001H01L2224/05022H01L2224/05124H01L2224/05147H01L2224/05572H01L2224/056H01L2924/00014
Inventor 王俊恒
Owner CHIPMOS TECH INC
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