Method and System For A Variable Frequency SDRAM Controller

Abstract

A method for providing a variable frequency clock for a SDRAM. First, receiving a clock with a fixed frequency and a plurality of signals, wherein each the signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals. Second, extracting a plurality of proper positions from the signals, wherein each low level of each the signal corresponds to a proper position. Third, amending the frequency of the clock such that each the proper position corresponds to a rising edge of the clock.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] Use of SDRAM is nowadays a very popular feature of the system in which large external buffer is necessary. Therefore, the SDRAM controller becomes a fundamental block of the ASIC design for a digital system. A new method to control the SDRAM is presented here, in which a non-regular frequency clock or control signals are involved to best fit timing requirement of a standard SDRAM. As a result, the most efficient timing to access a SDRAM is achieved. [0003] 2. Description of the Prior Art [0004] The conventional way to control a SDRAM is using a fix frequency clock as reference, generating all clock-based control signals such as RAS_, CAS_, MA according to this reference clock (see FIG. 1). This is a readily easy and straightforward way to use SDRAM. The fix frequency is constrained and decided by both system bandwidth requirement and working frequency of the logic circuit within an ASIC. To meet some SDRAM's timing ...

AI Technical Summary

Benefits of technology

[0005] The invention provides a method for providing a variable frequency clock for a SDRAM. The method comprises the following steps: (1) receiving a clock with a fixed frequency and a plurality of signals, wherein each the signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals; (2) extracting a plurality of proper positions from the signals, wherein each low level of each the signal corresponds to a proper position; and (3) amending the frequency of the clock such that each the proper position corresponds to a rising edge of the clock. Herein, each the proper position could located at the center of corresponding the low level; each the proper position could be located at a safety region around the center of corresponding the low level; and each the proper position could be located at a safety region inside corresponding the low level. Further, the step of amending the frequency of the clock is performed by the following steps chosen from the group consisting of the following: multiply frequency, divide frequency, mix the clock with at least one higher frequency clock, using doubled edges of the clock, using and the combination thereof.

[0006] Th

Problems solved by technology

Resolution of Tcyc may not be fine enough to generate the best fitting control waveforms to the SDRAM.

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