Vertical misfet manufacturing method, vertical misfet, semiconductor memory device manufacturing method, and semiconductor memory device
a manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, basic electric elements, electrical appliances, etc., can solve the problems of increasing leakage current (off current), complete depletion of channel forming regions, etc., and achieve the effect of reducing the area occupied by transistors and reducing cell siz
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Benefits of technology
Problems solved by technology
Method used
Image
Examples
first embodiment
[0055] In this embodiment, the present invention is applied to a DRAM constituting a memory cell that is composed of one memory cell selecting MISFET and one capacitor, and a manufacturing method thereof will be described in order of process step with reference to FIGS. 1 to 24.
[0056]FIG. 1 is a plan view of a semiconductor substrate (hereinafter, simply referred to as “substrate”) 1 showing an area equivalent to approximately four memory cells, and FIG. 2 is a sectional view of the substrate 1 taken along the line A-A′ in FIG. 1. Note that the substrate 1 is made of p type mono-crystalline silicon although not particularly limited.
[0057] The memory cell is formed in the manner as follows. First, as shown in FIG. 3, a silicon oxide film 2 with a thickness of approximately 50 to 100 nm and a silicon nitride film 3 with a thickness of approximately 140 nm are deposited on the substrate 1 by a CVD method. Thereafter, the silicon nitride film 3 and the silicon oxide film 2 in a memory...
second embodiment
[0085] In this embodiment, the present invention is applied to a p channel and vertical MISFET, and the manufacturing method thereof will be described in order of process with reference to FIGS. 25 to 35.
[0086] First, as shown in FIG. 25, a silicon oxide film 20 with a thickness of approximately 200 nm is deposited on the substrate 1 by the CVD method, and subsequently a p type poly-crystalline silicon film (lower semiconductor layer) 21 having a thickness of approximately 300 nm and doped with boron is deposited on the silicon oxide film 20 by the CVD method. Thereafter, the thermal treatment of the substrate 1 is performed in an atmosphere containing a NH3 gas. By so doing, a thin silicon nitride film 22 with a thickness of approximately 1 to 2 nm is formed on the surface of the poly-crystalline silicon film 21. This silicon nitride film 22 functions as a barrier film for preventing the impurity (boron) in the poly-crystalline silicon film 21 from diffusing into the channel formi...
third embodiment
[0104] The case where the n channel vertical MISFET is applied to the memory cell of the DRAM provided with a capacitor has been described in the first embodiment by way of an example. However, the present invention is not limited to the n channel vertical MISFET and the memory cell structure provided with the capacitor. More specifically, the present invention can be applied to the single vertical MISFET.
[0105]FIG. 37 (plan view showing a region equivalent to four memory cells), FIG. 38 (sectional view taken along line A-A′ in FIG. 37), and FIG. 39 (sectional view taken along line B-B′ in FIG. 37) show an example of: forming an insulating film (silicon oxide film) on a semiconductor substrate 1; and forming a vertical MISFET thereon. Note that since the manufacturing method of this vertical MISFET is identical to that in the first embodiment except the step of forming the capacitor, the detailed description thereof will be omitted. However, the content to be its outline is describ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More