150 results about "Poly crystalline" patented technology

The object of the present invention is to miniaturize the area occupied by the element and to integrate a plenty of elements in a limited area so that the sensor element can have higher output and smaller size. In the present invention, higher output and miniaturization are achieved by uniting a sensor element using an amorphous semiconductor film (typically an amorphous silicon film) and an output amplifier circuit including a TFT with a semiconductor film having a crystal structure (typically a poly-crystalline silicon film) used as an active layer over a plastic film substrate that can resist the temperature in the process for mounting such as a solder reflow process. According to the present invention, the sensor element that can resist the bending stress can be obtained.

The present invention relates to a method and device for integrating solar cell on LCD panels for photovoltaic electricity generation for portable electronic devices. According to one embodiment of the present invention, the black matrix region on the color filter substrate in a LCD panel is replaced by a solar cell region. A lens array substrate is coupled between the light source layer and the TFT to focus the backlight to increase the solar cell layer area while maintaining high fill ratio of the LCD pixels. The solar cell material is selected from at least silicon, a single crystal silicon, poly-crystalline silicon, amorphous silicon, gallium arsenide, cadmium telluride, copper indium diselenide, organic/inorganic, or hybrid cells. The substrate material is selected from glass, metal, plastic or polymer.

Disclosed is a heat treatment system for semiconductor devices. The heat treatment system is used in a heat treatment process for semiconductor devices, such as a crystallization process for an amorphous silicon thin film or a dopant activation process for a poly-crystalline silicon thin film formed on a surface of a glass substrate of a flat display panel including a liquid crystal display (LCD) or an organic light emitting device (OLED). The heat treatment system transfers a semiconductor device after uniformly preheating the semiconductor device in order to prevent deformation of the semiconductor device during the heat treatment process, rapidly performs the heat treatment process under the high temperature condition by heating the semiconductor device using a lamp heater and induction heat derived from induced electromotive force, and unloads the semiconductor device after uniformly cooling the semiconductor device such that the semiconductor device is prevented from being deformed when the heat treatment process has been finished. The heat treatment system rapidly performs the heat treatment process while preventing deformation of the semiconductor device by gradually heating or cooling the semiconductor device.

A pad conditioner for a CMP polishing pad is disclosed that includes a substrate that has a matrixical arrangement of protrusions that have a layer of poly crystalline diamond on at least their top surfaces. The protrusions may have varying shapes and elevations and may comprise a first set of protrusions and a second set of protrusions, the first set of protrusions have a first average height and the second set of protrusions have a second average height, the first average height different from the second average height, a top of each protrusion in the first set of protrusions has a non-flat surface and a top of each protrusion in the second set of protrusions has a non-flat surface.

Ophthalmic surgical blades are manufactured from either a single crystal or poly-crystalline material, preferably in the form of a wafer. The method comprises preparing the single crystal or poly-crystalline wafers by mounting them and etching trenches into the wafers using one of several processes. Methods for machining the trenches, which form the bevel blade surfaces, include a diamond blade saw, laser system, ultrasonic machine, a hot forge press and a router. Other processes include wet etching (isotropic and anisotropic) and dry etching (isotropic and anisotropic, including reactive ion etching), and combinations of these etching steps. The wafers are then placed in an etchant solution which isotropically etches the wafers in a uniform manner, such that layers of crystalline or poly-crystalline material are removed uniformly, producing single, double or multiple bevel blades. Nearly any angle can be machined into the wafer, and the machined angle remains after etching. The resulting radii of the blade edges is 5-500 nm, which is the same caliber as a diamond edged blade, but manufactured at a fraction of the cost. A range of radii may be 30 to 60 nm, with a specific implementation being about 40 nm. The blade profile may have an angle of, for example, about 60°. The ophthalmic surgical blades can be used for cataract and refractive surgical procedures, as well as microsurgical, biological and non-medical, non-biological purposes. Surgical and non-surgical blades and mechanical devices manufactured as described herein can also exhibit substantially smoother surfaces than metal blades.

In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P⁺-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.

A semiconductor device has a semiconductor device chip with upper and lower terminal electrodes, and upper and lower frames bonded to the upper and lower terminal electrodes, respectively, with solder material, wherein the semiconductor device chip includes: a semiconductor layer of a first conductivity type; a diffusion layer of a second conductivity type, which is selectively formed in the semiconductor layer; a plurality of guard-ring layers of the second conductivity type, which are formed outside of the diffusion layer in the semiconductor layer; an insulating film formed on the semiconductor layer; and a field plate formed of a poly-crystalline silicon film embedded in the insulating film.

The invention discloses methods for the preparation of poly-crystaline materials such as glass-ceramics.

The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate. A thin film transistor substrate includes a substrate; a first thin film transistor disposed on the substrate, the first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode over the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor disposed on the substrate, the second thin film transistor including a second gate electrode, an oxide semiconductor layer over the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed over the first gate electrode and the second gate electrode and under the oxide semiconductor layer.

A method for crystallizing an amorphous semiconductor thin film using a non-metal seed epitaxial growth (NSEG) is provided. The method includes the steps of: forming a pair of non-metal seeds for inducing a crystallization of an amorphous semiconductor thin film at a predetermined distance on a transparent insulation substrate; depositing the amorphous semiconductor thin film on the insulation substrate; and heat-treating the insulation substrate to thereby epitaxially grow a poly-crystalline semiconductor thin film from the non-metal seeds, and to thus crystallize the amorphous semiconductor thin film. In the crystallization method, non-metal seeds are used instead of using crystallization induced metal to thereby epitaxially grow the poly-crystalline semiconductor thin film and to thus realize the amorphous semiconductor thin film without having metal pollution.

A precision mold insert and method for manufacturing angled or angled and bumpered multi-fiber ferrules. The precision mold insert includes an angled end face forming portion, one or more optional bumper forming portions, one or more fiber bores for receiving one or more fiber bore forming pins, and one or more guide pin holes for receiving one or more guide pin hole forming pins. A method for manufacturing a precision mold insert for molding angled or angled and bumpered multi-fiber ferrules utilizing electrical discharge machining (EDM) process and/or a poly crystalline diamond (PCD) grinding tool is provided. The mold insert is used to produce a multi-fiber ferrule having a pre-molded angled end face that is not machined, polished or otherwise altered subsequent to the molding process. The ferrule may also include bumpers for polishing end portions of optical fibers positioned within the fiber bores without altering the angled end face.

Disclosed are a method of fabricating a silicon quantum dot layer and a device manufactured using the same. A first capping layer is formed on a substrate, and a silicon-containing precursor layer is formed on the first capping layer. A second capping layer is formed on the silicon-containing precursor layer. The first capping layer, the silicon-containing precursor layer, and the second capping layer are irradiated to convert the silicon-containing precursor layer into a stack including a first poly-crystalline silicon layer, a silicon quantum dot layer on the first poly-crystalline silicon layer, and a second poly-crystalline silicon layer on the silicon quantum dot layer.

Provided are a poly crystalline silicon semiconductor device and a method of fabricating the same. Portions of a silicon layer except for gates are removed to reduce a parasitic capacitance caused from the silicon layer existing on gate bus lines. The silicon layer exists under the gates only, thus the parasitic capacitance is reduced and the deterioration and the delay of signals are prevented. Accordingly, the poly crystalline silicon semiconductor device, such as a thin film transistor, has excellent electric characteristics.

Embodiments of the invention generally relate to methods for fabricating photovoltaic devices, and more particularly to methods for in-situ cleaning of a solar cell substrates. In one embodiment, a method of manufacturing a solar cell device is provided. The method comprises exposing a single or poly crystalline silicon substrate to a wet clean process to clean the surfaces of the crystalline substrate, loading the crystalline silicon substrate into a processing system having a vacuum environment, exposing at least one surface of the crystalline silicon substrate to an in-situ cleaning process in the vacuum environment of the processing system, and forming one or more passivation layers on at least one surface of the crystalline silicon substrate in the processing system.

A method of fabricating poly crystalline silicon type thin film transistor is disclosed. In the method, before the step of re-crystallization of amorphous silicon to form polycrystalline silicon active pattern, a step for injecting predetermined amount of oxygen atom into the surface part of the amorphous silicon layer. By this addition of step, the surface part of the silicon layer is to be oxidized and the crystal defect in the interface between the gate insulating layer and poly crystalline silicon layer can be cured and the mobility of charge carrier can be improved in the channel of the thin film transistor.

The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate, and a display using the same. A display includes a first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode on the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor including a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer.

The invention discloses a method for improving the phosphorus concentration uniformity of doped polycrystalline or noncrystalline silicon chips. According to the method, a furnace tube is adopted for growth, phosphorane is introduced through three nozzle pipelines, and the top ends of the nozzle pipelines are arranged at the bottom, the middle and the top of a crystal boat respectively; gas is emitted from the top of the first nozzle pipeline; a plurality of lateral gas outlets are formed in each of the second and third nozzle pipelines at intervals; the diameters of the lateral gas outlets of each pipeline are gradually increased in a direction from the bottom end to the top end and adjusted by testing the phosphorus concentration of the monitored silicon chips at the fixed monitoring positions of the crystal boat; the positions of the lateral gas outlets are adjusted by testing a phosphorus concentration curve along the whole crystal boat. The invention further discloses a structure for improving the phosphorus concentration uniformity of the doped polycrystalline or noncrystalline silicon chips. According to the method and the structure, the phosphorus concentration uniformity of the silicon chips can be improved and the production cost can be reduced.

Provided is a silicon thin film transistor (TFT) including: a substrate; a silicon channel layer formed on the substrate with a source and a drain on both sides thereof; a gate insulating layer formed on the silicon channel layer; and a gate formed on the gate insulating layer, wherein the gate insulating layer has a structure including an HfO_x film. The TFT has a low leakage current.