Multilayer capacitor, manufacturing method thereof

Abstract

A multilayer capacitor 10 comprising a dielectric body 12 formed by stacking a plurality of dielectric layers 12a and 12b having an approximately rectangular parallelepiped shape; an internal layer portion 17 in which pluralities of first internal conductor layers 21 and second internal conductor layers 22 to be set at different electric potentials each other are stacked alternately in said dielectric body 12 via said dielectric layer 12a as mutually overlapping in stacking direction Z to form an internal electrode circuit of a capacitor; an external layer portion 19a and 19b in which pluralities of first external conductor layers 23 and second external conductor layers 25 to be set at different electric potentials which are not overlapping in stacking direction Z, are stacked in said dielectric body 12 via said dielectric layer 12b, the external layer portions being adjacent to at least any of both end faces of said internal layer portion 17 in stacking direction Z; and a first terminal electrode 31 and a second terminal electrode 32 to be set at different electric potentials each other are formed at least on a side face parallel to stacking direction Z of side faces of said dielectric body. Each of the first terminal electrodes 31 are connected with at least one of said first internal conductor layer 21 and a plurality of said first external conductor layers 23; and each of the second terminal electrodes 32 are connected with at least one of said second internal conductor layer 22 and a plurality of said second external conductor layers 25. The dielectric layer 12b positioned at said external layer portions 19a and 19b comprises, in an area of overlapping a pair of said first external conductor layers 23 or a pair of said second external conductor layers 25 adjacent to said dielectric layer 12b, a plurality of pin hole conducting portions 20 connecting a pair of said first external conductor layers 23 or a pair of said second external conductor layers 25 each other adjacent to said dielectric layer 12b, in stacking direction Z.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to multilayer capacitor greatly reducing the equivalent serial inductance (ESL) and production method thereof, more particularly relates to a multilayer capacitor used as a decoupling capacitor and manufacturing method thereof.[0003]2. Description of the Related Art[0004]In recent years, while advances have been made in reducing the voltage of power sources used for supplying power to large-scale integrated circuits (LSI's) and other integrated circuits, the load current has increased.[0005]Therefore, it has become extremely difficult to keep fluctuations in the power source voltage to within tolerances when faced with rapid changes in the load current. Therefore, a decoupling capacitor (for example two-terminal structure multilayer ceramic capacitor) is now being connected to a power source. At the time of transitory fluctuation in the load current, current is supplied from this multilayer...

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