Glitch-free clock switching circuit
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[0015]The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
[0016]FIG. 3 shows a clock switching circuit 200 according to an embodiment of the invention. The clock switching circuit 200 comprises a clock switching control device 210, an AND logic gate 296, a multiplexer 260, clock gate control units 230 and 250, and synchronization devices 221 and 222. The clock switching circuit 200 receives a first clock signal clk_a and a second clock signal clk_b and outputs a third clock clk_a_gated signal or a fourth clock signal clk_b_gated as a clock output signal clk_out according to a clock switching signal. The third clock signal clk_a_gated corresponds to the first clock signal clk_a and the fourth clock signal clk_b_gated correspon...
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