Improved SiCOH Hardmask with Graded Transition Layers
a transition layer and hardmask technology, applied in semiconductor devices, semiconductor/solid-state device details, chemistry apparatus and processes, etc., can solve the problems of oxidizing species, chip interconnect structures made in low-k dielectric materials may fail or degrade, and reliability problems associated with these structures
Inactive Publication Date: 2015-01-29
INT BUSINESS MASCH CORP +1
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Benefits of technology
The improved hardmask structure achieves smooth and uniform profiles for contact vias and electrical contacts, enhancing reliability and reducing the need for multiple process steps and tool sets, thereby improving the performance and reliability of BEOL metallization.
Problems solved by technology
However, reliability problems are associated with these structures.
During integration, reliability stress, or extended use, a chip interconnect structure made in a low-k dielectric material may fail or degrade due to poor adhesion, moisture uptake, and various stress migration between the metal liner / metal and the low-k dielectric material.
These reliability issues result from defects in the porous low-k dielectric material and the metal liner / metal of the interconnects, which results in oxidizing species such as H2O or O2 interacting with the metal.
The varying compositions and material properties of the various deposition layers used in conventional hardmasks (oxide adhesion layer, transitional layer, low-k / UK dielectric layer, and layers of oxygen-containing organosilicon compounds) make it difficult to form defect free lines and vias.
During the etching process, the various hardmask layers react differently to the etchants, resulting in interconnects that have a rough or uneven profile (e.g., undercut profile) that negatively affects performance.
In addition to these integration problems, conventional processes used to form hardmasks involve multiple tool sets and several steps in which the process conditions must be altered.
Method used
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[0018]Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description and drawings, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
[0019]The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating an improved SiCOH hardmask with graded transition layers and having an improved profile for...
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A structure and method for fabricating an improved SiCOH hardmask with graded transition layers having an improved profile for forming sub-20 nm back end of the line (BEOL) metallized interconnects are provided. In one embodiment, the improved hardmask may be comprised of five layers: an oxide adhesion layer, a graded transition layer, a dielectric layer, an inverse graded transition layer, and an oxide layer. In another embodiment, the improved hardmask may be comprised of four layers; an oxide adhesion layer, a graded transition layer, a dielectric layer, and an oxide layer. In another embodiment, a method of forming an improved hardmask may comprise a continuous five step plasma enhanced chemical vapor deposition (PECVD) process utilizing a silicon precursor, a porogen, and oxygen. In yet another embodiment, a method of forming an improved hardmask may comprise a continuous four step PECVD process utilizing a silicon precursor, a porogen, and oxygen.
Description
FIELD OF THE INVENTION[0001]The present invention relates generally to the fabrication of integrated circuits, and more particularly, to a structure and method for fabricating an improved SiCOH hardmask with graded transition layers and having an improved profile for forming sub-20 nm back end of the line (BEOL) metallized interconnects.BACKGROUND OF INVENTION[0002]As integrated circuit (IC) features continue to be scaled down to deep submicrometer (μm) dimensions (0.05-0.20 μm), metal interconnects become a bottleneck for continued IC performance improvement. Within a typical interconnect structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered interconnect schemes, such as, for example, dual damascene wiring structures based on copper. Copper based interconnect structures are desirable over previously used aluminum int...
Claims
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IPC IPC(8): H01L23/532H01L21/768H01L23/522
CPCH01L23/53295H01L23/5226H01L21/76802H01L21/02126H01L21/02164H01L21/02203H01L21/02211H01L21/02216H01L21/02274H01L21/0332H01L21/31144H01L21/76801H01L21/76832H01L21/76834H01L23/5329H01L2924/0002H01L2924/00
InventorANGYAL, MATTHEW S.LOQUET, YANNICK S.MIGNOT, YANN A.NGUYEN, SON V.SANKARAPANDIAN, MUTHUMANICKAMSHOBHA, HOSADURGA
OwnerINT BUSINESS MASCH CORP