Circular vias and interconnect-line ends

a technology of interconnecting lines and vias, which is applied in the direction of cad circuit design, instrumentation, and semiconductor/solid-state device details, etc., can solve the problems of not being able to explore diagonal routing paths consistently, affecting the design of the layer, and affecting the performance of the layer

Inactive Publication Date: 2005-12-13
CADENCE DESIGN SYST INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

IC designs often penalize non-preferred direction wiring on a layer.
Also, in this wiring model, the majority of the wires can only make 90° turns.
While some commercial routers today might allow an occasional diagonal jog, these routers do not typically explore diagonal routing paths consistently when they are specifying the routing geometries of the interconnect lines.
Consequently, they arbitrarily limit the locations of interconnect lines and impose arbitrary spacing between the items in the layout.
These arbitrary limits increase the size and efficiency of a design.
Such IC layouts and IC's do not efficiently use the available spacing on the interconnect layers, and this adversely affects the size and efficiency of the layouts and the IC's.

Method used

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  • Circular vias and interconnect-line ends
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  • Circular vias and interconnect-line ends

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Embodiment Construction

[0071]In the following description, numerous details are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail.

I. Non-Preferred Direction Architecture

[0072]Some embodiments of the invention utilize non-preferred-direction (“NPD”) wiring models for designing IC layouts. A NPD wiring model does not specify a single preferred routing direction for at least one of its interconnect layers. (In the discussion below, the terms interconnect layer is interchangeably used with the terms metal or wiring layer.)

[0073]A NPD wiring model has at least one NPD interconnect layer that has more than one preferred routing direction. In other words, each NPD interconnect layer has at least two routing directions that are e...

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Abstract

Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ. Some embodiments of the invention provide interconnect lines that have non-rectangular ends. In some embodiments, the interconnect-line ends are partial octagons, hexagons, and/or circles. Also, some embodiments provide Steiner points that are not rectangular. In some embodiments, the Steiner points are octagonal, hexagonal, or circles.

Description

[0001]This patent application claims the benefit of the earlier-field U.S. Provisional Patent Application entitled “Interconnect Method, Apparatus, and Architecture for Integrated Circuits and Integrated-Circuit Layouts”, having Ser. No. 60 / 295,735, and filed Jun. 3, 2001; and U.S. Provisional Patent Application entitled “Interconnect Method, Apparatus, and Architecture for Integrated Circuits and Integrated-Circuit Layouts”, having Ser. No. 60 / 298,146, and filed Jun. 12, 2001; and U.S. Provisional Patent Application entitled “Method and Apparatus for Routing a Set of Nets”, having serial number 60 / 351,459, and filed Jan. 22, 2002.FIELD OF THE INVENTION[0002]The invention is directed towards circular vias and interconnect-line ends.BACKGROUND OF THE INVENTION[0003]An integrated circuit (“IC”) is a semiconductor device that includes many electronic components (e.g., transistors, resistors, diodes, etc.). These components are often interconnected to form multiple circuit components (e...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06F17/50H01L23/52H01L23/522H01L23/528
CPCG06F17/5068H01L23/5226H01L23/528H01L2924/0002H01L2924/00G06F30/39
Inventor TEIG, STEVENFUJIMURA, AKIRACALDWELL, ANDREW
Owner CADENCE DESIGN SYST INC
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