Chip encapsulation structure and its making method
A technology of chip packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc.
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[0011] Please also refer to Figure 1A and Figure 1B , Figure 1A It is a schematic cross-sectional view of a chip packaging structure with a planar annular reinforcement conforming to the features of the present invention, Figure 1B It is a schematic cross-sectional view of a chip packaging structure with a turning ring reinforcement conforming to the features of the present invention. As shown in the figure, the chip packaging structure 100 includes a carrier 102 , a chip 104 , a reinforcement and a glue 108 . The carrier 102 is, for example, a substrate, and the chip 104 is, for example, a low dielectric constant (low-K) chip. The chip 104 has an upper surface 104a, a lower surface 104b, and an outer sidewall 104c, wherein the lower surface 104b is configured on the carrier 102, and the upper The surface 104a is electrically connected to the carrier 102 through the wire 110 . The reinforcement covers the edge of the upper surface 104a to protect the edge. The way the r...
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