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Chip encapsulation structure and its making method

A technology of chip packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc.

Active Publication Date: 2009-04-15
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to provide a chip packaging structure and its manufacturing method, which overcomes the defect that the edge part of the existing low dielectric constant chip is easily broken, effectively protects the edge of the low dielectric constant chip and prevents it from being damaged by collision or vibration. broken

Method used

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  • Chip encapsulation structure and its making method
  • Chip encapsulation structure and its making method
  • Chip encapsulation structure and its making method

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Embodiment Construction

[0011] Please also refer to Figure 1A and Figure 1B , Figure 1A It is a schematic cross-sectional view of a chip packaging structure with a planar annular reinforcement conforming to the features of the present invention, Figure 1B It is a schematic cross-sectional view of a chip packaging structure with a turning ring reinforcement conforming to the features of the present invention. As shown in the figure, the chip packaging structure 100 includes a carrier 102 , a chip 104 , a reinforcement and a glue 108 . The carrier 102 is, for example, a substrate, and the chip 104 is, for example, a low dielectric constant (low-K) chip. The chip 104 has an upper surface 104a, a lower surface 104b, and an outer sidewall 104c, wherein the lower surface 104b is configured on the carrier 102, and the upper The surface 104a is electrically connected to the carrier 102 through the wire 110 . The reinforcement covers the edge of the upper surface 104a to protect the edge. The way the r...

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Abstract

This invention discloses one chip sealing structure and its process method, wherein, the structure comprises load part, chip, fixing object and glue part; the method comprises the following steps of setting chip down surface onto load and fixing the cover onto chip edge for protection and bonding the chip surface and load part and finally forming glue covering chip, fix part and load.

Description

【Technical field】 [0001] The invention relates to a chip packaging structure and a manufacturing method thereof, in particular to a chip packaging structure with a reinforcement and a manufacturing method thereof. 【Background technique】 [0002] In the prior art, because of the fragile material of the chip in the chip package structure, the edge of the upper surface of the chip is prone to cracking, and this situation is especially likely to occur on a low dielectric constant (low-K) chip. Due to better telecommunications performance and faster signal transmission speed, low dielectric constant chips are widely used in the industry. Therefore, how to solve the problem that the edge of the chip is easily broken has become an important research topic for those skilled in the art. 【Content of invention】 [0003] The purpose of the present invention is to provide a chip packaging structure and its manufacturing method, which overcomes the defect that the edge part of the exis...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/49H01L21/56H01L21/60
CPCH01L2924/01019H01L2224/4899H01L2224/48227
Inventor 丁一权
Owner ADVANCED SEMICON ENG INC