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Chip package structure and manufacturing method thereof

A chip packaging structure and chip technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve problems such as chip fragility, and achieve the effect of solving fragmentation

Active Publication Date: 2009-03-18
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a chip packaging structure and its manufacturing method, which overcomes the defect that the edge part of the existing low dielectric constant chip is easily broken, effectively protects the edge of the low dielectric constant chip and prevents it from being damaged by collision or vibration. broken

Method used

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  • Chip package structure and manufacturing method thereof
  • Chip package structure and manufacturing method thereof

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Embodiment Construction

[0012] Please refer to Figure 1A , is a schematic cross-sectional view of a chip packaging structure conforming to the features of the present invention. As shown in the figure, the chip packaging structure 100 includes a carrier 102 , a chip 104 , a first colloid and a second colloid 108 . The carrier 102 is, for example, a circuit substrate, and the chip 104 is, for example, a low dielectric constant (low-K) chip. The chip 104 has an upper surface 104a, a lower surface 104b, and an outer sidewall 104c, wherein the lower surface 104b is disposed on the carrier 102, The upper surface 104a is electrically connected to the carrier 102 through the circuit 110 . The first glue covers the edge of the upper surface 104a. Such as Figure 1A As shown, the first colloid is a planar colloid film layer 106a protruding from the edge to protect the edge. The material of the first colloid has, for example, a low modulus (module) material property, so that the first colloid can absorb the ...

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Abstract

The invention discloses one kind of a chip package structure and its manufacturing method. The chip package structure includes a vector, a chip, a first colloid and a second colloid. The manufacturing method is: firstly, it installs the undersurface of chip on the vector and interfaces the super-surface of chip with the vector, and then it forms the first colloid on the super-surface edge of the chip to protect the edge, finally, it forms the second colloid to cover the chip, the first colloid and the partial vector. This invention protects the on-surface edge of the chip by using the first and the second colloid. In the existing chip technology, it effectively solves the chip fragmentation problem on the super-surface edge because of the fragile material.

Description

【Technical field】 [0001] The invention relates to a chip packaging structure and a manufacturing method thereof, in particular to a low dielectric constant chip packaging structure and a manufacturing method thereof. 【Background technique】 [0002] In the prior art, because of the fragile material of the chip in the chip package structure, the edge of the upper surface of the chip is prone to cracking, and this situation is especially likely to occur on a low dielectric constant (low-K) chip. Due to better telecommunications performance and faster signal transmission speed, low dielectric constant chips are widely used in the industry. Therefore, how to solve the problem that the edge of the chip is easily broken has become an important research topic for those skilled in the art. 【Content of invention】 [0003] The purpose of the present invention is to provide a chip packaging structure and its manufacturing method, which overcomes the defect that the edge part of the e...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/49H01L21/56H01L21/60
CPCH01L2924/01019H01L2224/4899H01L2224/48227
Inventor 丁一权
Owner ADVANCED SEMICON ENG INC