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High access efficiency interface circuit and method

A technology of access efficiency and interface circuit, applied in the direction of electrical digital data processing, instrument, input/output to record carrier, etc., can solve the problems of poor access efficiency and so on

Active Publication Date: 2009-09-09
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The main control device 24 must wait until the data is written into the external memory from the corresponding write buffer 45 through the external interface 10, that is, the main control device 24 must wait before the data can be "validly" read, so the access efficiency is not good

Method used

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  • High access efficiency interface circuit and method
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Embodiment Construction

[0019] Having summarized the various features of the invention, reference is now made to the detailed description of the invention as illustrated in the illustrations. The present invention will be described with reference to the relevant figures, but it is not intended to limit the present invention to the embodiments disclosed in the description. On the contrary, modifications and equivalents are also covered by the present invention if they are included in the spirit and scope of the invention defined by the appended claims.

[0020] It should be noted that the drawings listed herein are used to illustrate certain features and aspects of the embodiments of the present invention. From the description provided herein it will be apparent that various alternative embodiments and implementations can be implemented which are within the scope and spirit of the invention.

[0021] refer to figure 2 , which shows a block diagram of an embodiment of the present invention. figure...

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Abstract

The present invention discloses an interface circuit and method with high access efficiency. The interface circuit includes a plurality of bidirectional buffers and logic circuits. In response to a read request from a system component, it is configured to confirm that the requested data is currently present. is located in the bi-directional buffer and is designated to be written from the bi-directional buffer to an external memory, wherein the logic is further configured to supply the data from the bi-directional buffer to the requesting system element, It is not necessary to write the data into the external memory first, thereby improving the data access efficiency of the memory.

Description

technical field [0001] The invention relates to a bus arbitration of a computer system, in particular to a memory interface circuit and method with high access efficiency. Background technique [0002] A memory controller is designed to interface various types of memory on behalf of one or more requestors (eg, processors, peripheral devices, etc.). Typically, a memory controller is used to provide certain latency and bandwidth characteristics. It is often desirable to provide low-latency and high-band access to the memory. However, optimization for lower latency may reduce the frequency band. Likewise, optimization of boost frequency bands may result in increased latency. Therefore, designers of memory controllers often have to make a trade-off between low latency and high band characteristics. [0003] The latency and bandwidth characteristics of the memory controller can be preselected. For example, a memory controller may be optimized to match processor accesses base...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06G06F13/16
Inventor 查理斯·雪洛
Owner VIA TECH INC