Software controllable Cache implementing method facing flush type application

An implementation method and embedded technology, applied in the direction of instruments, electrical digital data processing, memory systems, etc., can solve the problems of poor controllability and low utilization rate, and achieve the effect of convenient and efficient management

Active Publication Date: 2010-03-24
SOUTHEAST UNIV
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AI Technical Summary

Problems solved by technology

However, the traditional Cache for embedded applications only uses a single hardware replacement algorithm to predict the locality of access, and does not fully consider the characteristics of software applications. The hardware and software mechanisms related to data storage are separated from each other, thus making Cache The design has the disadvantages of low utilization rate and poor controllability

Method used

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  • Software controllable Cache implementing method facing flush type application
  • Software controllable Cache implementing method facing flush type application
  • Software controllable Cache implementing method facing flush type application

Examples

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Embodiment Construction

[0038] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments.

[0039] Explanation of labels in the figure: ARM7TDMI embedded microprocessor 1, on-chip high-speed cache Cache 2, off-chip synchronous dynamic random access memory 3, storage subsystem performance simulation module 4, Cache controller 5, tag table sub-module 6, storage copy sub-module 7, The control logic sub-module 8, the decoding unit 9, the Cache storage unit 10, the replacement candidate row selection unit 11, and the data I / O unit 12.

[0040] figure 1 It is a block diagram of the storage subsystem of the ARM7TDMI embedded microprocessor. The storage subsystem includes ARM7TDMI embedded microprocessor 1, on-chip cache Cache2, off-chip synchronous dynamic random access memory 3. Among them, ARM7TDMI embedded microprocessor 1 is tightly coupled with on-chip cache Cache2; off-chip synchronous dynamic random access memory 3 and on-chip The high-speed...

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Abstract

The invention relates to a realizing method for a controllable software Cache facing to embedded application; based on the traditional embedded Cache structure, a Cache controller is added to realizethe following three operations: the data which has a large expanse and a uniformly distributed life period is accessed; a copy in the Cache is preserved; the data causing the partial descending of thepre-fetching time of the Cache is directly communicated with an external memory through a processor; the data which is frequently accessed at a certain time stays in the Cache preferentially in the effective life period. The method includes the following steps: an application procedure is operated under the condition of closing the caching function of the Cache for obtaining an access record; a mark data block is selected according to the access record; the content of a mark information list is generated according to the characteristics of the mark data block and is loaded into the Cache controller; the operation process of the Cache is controlled; wherein, the content of the mark information list can be dynamically collocated for software in the running process of the system.

Description

Technical field [0001] The invention belongs to the field of embedded design, in particular to an implementation method of software controllable Cache for embedded applications, which can be applied to the optimization of data storage in the design of high-performance embedded system chips. Background technique [0002] In the design of modern high-performance embedded systems, Cache effectively solves the problem of speed matching between the processor and the main memory. Compared with the processor frequency which is increasing by more than 40% per year, the speed of the memory is only increasing by about 11% per year. It is foreseeable that as the speed difference between the processor and the main memory becomes larger and larger, the design of the Cache will also become one of the key factors that determine the overall performance of the system. However, the traditional Cache for embedded applications only uses a single hardware replacement algorithm to predict the localit...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F12/0875
Inventor 刘波王学香杨军刘新宁
Owner SOUTHEAST UNIV
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