Release method, system and logic module for buffered address

Abstract

The invention provides a method for releasing a cache address, which includes the steps as follows: when a message is transmitted to a CPU from a logic module, the CPU inquires about the packet information from the logic module, then in light of the packet information, the CPU reads the message from the logic module; after reading the message, the CPU reads the packet information corresponding tothe message from the logic module which then releases the cache address contained in the packet information. The invention also provides a logic module and a cache address releasing system. The invention can ensure that the cache address is released appropriately, thus preventing the occurrence of releasing the cache address in a wrong way.

Description

technical field [0001] The invention relates to data cache technology, in particular to a cache address release method, system and logic module. Background technique [0002] In data communication technology, after a logic module (such as CPU_RX module) receives a message from the outside, it will first apply for a cache address to cache the message. If the message is an ordinary data message, it will pass the data channel to the message Send out; if the message is a protocol message, send the message to the CPU through the control channel. Regardless of whether it is a data message or a protocol message, after the message is sent, the cache address previously applied for the message needs to be released. This article mainly describes the address release operation of protocol packets. [0003] FIG. 1 shows a schematic structural diagram of a logic module in the prior art. The process of requesting and releasing a protocol message address in the prior art will be described ...

AI Technical Summary

Problems solved by technology

In this case, if the interface between the CPU and the logic module is abnormal (such as instantaneous and unpredictable external interference such as lightning strikes, or information loss due to excessive CPU link traffic at the moment of the network, etc.) or a CPU release error, It will cause the leakage or wrong release of the cache address in the logic module, and eventually lead to the CPU channel being blocked or an error packet.

For example, assuming that the cache address contained in the packet information B1 stored in the FIFO queue is B, if the CPU releases the cache address B by mistake when the cache address A should be released, and the message receiving module sends New data is rewritten in the cache address B that was released by mistake. Then, when the CPU next reads data from the cache address B according to the packet information B1 in the FIFO queue, what is read will be the message receiving module that will be rewritten later. The written data is not the original data corresponding to the package information B1, so there is a phenomenon of wrong package

In addition, when the interface between the CPU and the logic module is abnormal, it is likely to cause the loss of the address release command issued by the CPU, so that the cache address that should be released cannot be released. If things go on like this, the available cache addresses will gradually decrease. , when no cache address is available, the CPU channel will be blocked

Images