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Method of inspecting printed wiring board and printed wiring board

A technology for printed circuit boards and inspection methods, which is applied in the fields of printed circuit, printed circuit, and printed circuit manufacturing, and can solve the problems that the inspection results cannot accurately reflect the actual state of the product, and the manufacturing tolerance is large.

Inactive Publication Date: 2008-07-02
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in the case where an inspection method using such an inspection pattern is applied, when the manufacturing tolerance is large, there is a possibility that the inspection result may not accurately reflect the actual state of the product

Method used

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  • Method of inspecting printed wiring board and printed wiring board
  • Method of inspecting printed wiring board and printed wiring board
  • Method of inspecting printed wiring board and printed wiring board

Examples

Experimental program
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Embodiment Construction

[0028] Various embodiments according to the present invention will be described below with reference to the accompanying drawings.

[0029] First, the printed wiring board 1 and the inspection method of the printed wiring board 1 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 9 .

[0030] FIG. 1 shows the entire printed wiring board 1 . For example, a printed wiring board 1 is a laminated board (called a work) as a manufacturing unit, which includes a plurality of product parts 2 as products. The individual product parts 2 are cut out of the printed circuit board 1 in a subsequent step and mounted on the electronic device as a system board.

[0031] The printed wiring board 1 includes samples 3 , for example, four samples, and the samples are located at the peripheral portion of the printed wiring board 1 outside the product portion 2 . The sample 3 was integrally laminated together with the product part 2, and its l...

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PUM

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Abstract

According to one embodiment, in the inspection method of a printed wiring board (1, 41, 61), a printed wiring board (1) equipped with an outer layer surface (5a, 5b) and an inner layer surface (5c, 5f) is prepared for inspection , 41, 61). The printed circuit board (1, 41, 61) comprises a land area (9) provided on the outer surface (5a, 5b), a passage (10) extending from the land area (9) to the inner surface (5c, 5f), and the inner layer pattern (21) provided on the inner layer surface (5c, 5f), wherein when the path displacement in the printed wiring board (1, 41, 61) is within the tolerance range, the inner layer pattern (21) Electrically connected to via (10). The conduction state between the layer area (9) and the inner layer pattern (21) is detected.

Description

technical field [0001] One embodiment of the present invention relates to a printed wiring board and a method for inspecting a printed wiring board. Background technique [0002] In the manufacture of multilayer printed wiring boards, the surface of the inner layer is sometimes shifted relative to the surface of the outer layer (this shift will be referred to as "via shift"). In this case, when a passage for forming an interlayer connection to a land region on the surface of the inner layer (hereinafter referred to as an inner layer land region) is formed on the surface of the outer layer, the passage is shifted relative to the land region of the inner layer. bit. "Zaochi" can occur when the pathway is displaced relative to the inner laminar region. [0003] The so-called "Zaochi" is a detrimental state in which a part of the pathway is located outside the target laminar region, and this part of the pathway has absolutely no relationship with the laminar region. A "target...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H05K13/08G01R31/02
CPCG01R31/2805H05K1/0268H05K1/115H05K3/4644H05K3/4679H05K2201/09509H05K2203/162
Inventor 唐沢纯铃木大悟玉井定广
Owner KK TOSHIBA