Unlock instant, AI-driven research and patent intelligence for your innovation.
Method for evaluating semiconductor wafer
What is Al technical title?
Al technical title is built by PatSnap Al team. It summarizes the technical point description of the patent document.
An evaluation method, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device testing/measurement, electric solid-state devices, etc., can solve problems such as difficulty, long time, inefficiency, etc., and achieve the effect of good efficiency
Active Publication Date: 2009-09-09
SHIN-ETSU HANDOTAI CO LTD
View PDF2 Cites 11 Cited by
Summary
Abstract
Description
Claims
Application Information
AI Technical Summary
This helps you quickly interpret patents by identifying the three key elements:
Problems solved by technology
Method used
Benefits of technology
Problems solved by technology
[0013] However, unlike polished wafers (PW) and other wafers such as SOI wafers, which have been in high demand in recent years, for example, since there is an insulating layer, that is, a BOX layer, when evaluating this SOI wafer, it is simply applied to conventional wafers. It is difficult to evaluate the inside of the active layer of the SOI wafer by using the method of utilizing the above-mentioned junction leakage current characteristics in the case of known polished wafers.
[0014] In addition, it takes a long time to obtain the result by actually making a device for evaluation, and the feedback to the wafer process is also time-consuming and inefficient.
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more
Image
Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
Click on the blue label to locate the original text in one second.
Reading with bidirectional positioning of images and text.
Smart Image
Examples
Experimental program
Comparison scheme
Effect test
Embodiment 1
[0079]Using the evaluation method of the present invention, evaluation of semiconductor wafers was carried out.
[0080] As the wafer to be measured, a silicon-on-insulator (SOI) wafer with a diameter of 200 mm and a crystal orientation of was used, both of the base wafer and the SOI layer being of P-type conductivity. In addition, boron is used as a dopant in order to make it P-type. Also, the thicknesses of the SOI layer and the BOX layer are about 13 and 1 μm, respectively.
[0081] Also, the SOI layer was intentionally contaminated with iron (Fe) in advance. Prepare 1×10 11 / cm 2 (exist figure 2 Use 1.E+11 to represent 1×10 11 , the same below), 5×10 11 / cm 2 , 1×10 13 / cm 2 , 1×10 14 / cm 2 of SOI wafers.
[0082] This SOI wafer was subjected to high-temperature oxidation at 1000° C. to form an oxide film of 1 μm on the surface of the SOI wafer.
[0083] After that, use a photomask (a plurality of 500μm square patterns arranged at 1mm intervals) to perform a...
Embodiment 2
[0089] Except that the measuring machine is a machine for measuring deep-level transient spectroscopy (DLS-83D manufactured by Semilab (Semilab) Co., Ltd.), use the same procedure as in Example 1 to evaluate intentional contamination with iron (Fe). 5×10 11 / cm 2 Concentration after sample SOI wafer results, obtained image 3 According to the measurement data shown, according to the measurement data library (reference (reference) measurement results), the peak was identified as iron, and the amount of contamination was evaluated as 5×10 11 / cm 2 .
[0090] That is, according to the evaluation method of the present invention, it is possible to accurately determine the type and amount of contamination of metal contamination.
[0091] As mentioned above, according to the evaluation method of the semiconductor wafer of the present invention, there is no need to perform difficult processing specially, because it is only necessary to form adjacent diffusion parts to form PN junc...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More
PUM
Login to View More
Abstract
The present invention provides a method for evaluating a semiconductor wafer, including at least: forming an oxide film on a front surface of a semiconductor wafer; partially removing the oxide film to form windows at two positions; diffusing a dopant having a conductivity type different from a conductivity type of a semiconductor as an evaluation target through the windows at the two positions and forming diffused portions in the semiconductor as the evaluation target to form PN junctions; and performing leakage current measurement and / or DLTS measurement in a part between the two diffused portions to evaluate the semiconductor wafer. As a result, there is provided the method for evaluating a semiconductor wafer that can perform junction leakage current measurement or DLTS measurement to easily evaluate a quality of the inside of the semiconductor wafer. In particular, the invention provides a method that can evaluate not only a PW or an EPW but also the inside of an SOI layer of an SOI wafer.
Description
technical field [0001] The present invention relates to a method of evaluating a semiconductor wafer such as a silicon wafer or a silicon on insulator (SOI) wafer, for example. Background technique [0002] In recent years, silicon-on-insulator (SOI) wafers have a silicon-on-insulator (SOI) structure in which a silicon active layer has been formed on an electrically insulating silicon oxide film. Excellent in performance, low power consumption, high withstand voltage, and environmental resistance, it is particularly valued as a high-performance large-scale integrated circuit (LSI) chip for electronic devices. This is because in the SOI wafer, between the base wafer (base wafer) and the silicon active layer (hereinafter also referred to as the SOI layer), there is an insulator, that is, a buried oxide layer (hereinafter sometimes referred to as the BOX layer), so it is formed in the Electronic devices on the SOI layer have great advantages such as high withstand voltage and ...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More
Application Information
Patent Timeline
Application Date:The date an application was filed.
Publication Date:The date a patent or application was officially published.
First Publication Date:The earliest publication date of a patent with the same application number.
Issue Date:Publication date of the patent grant document.
PCT Entry Date:The Entry date of PCT National Phase.
Estimated Expiry Date:The statutory expiry date of a patent right according to the Patent Law, and it is the longest term of protection that the patent right can achieve without the termination of the patent right due to other reasons(Term extension factor has been taken into account ).
Invalid Date:Actual expiry date is based on effective date or publication date of legal transaction data of invalid patent.
Login to View More 
Login to View More