LDPC code decoder

An LDPC code and decoder technology, applied in the field of wireless digital communication, can solve the problems of increasing hardware resources in proportion to the number of supported code rates, inability to flexibly adapt to changes in code rates, and fixed decoding structure, achieving strong operability. performance and flexibility, improving design efficiency, and reducing complexity

Inactive Publication Date: 2009-12-02
FUDAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the current communication system, the decoding structure is too fixed, it cannot flexibly adapt to the change of the code rate, and the hardware resources increase proportionally to the number of supported code rates, which is not conducive to the multiplexing of resources.

Method used

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  • LDPC code decoder
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Embodiment Construction

[0023] The structure of the LDPC code decoder of the present invention is as figure 1 As shown, it includes an input cache module, a control module, an operation processing module, an intermediate memory, a microinstruction memory, a switching network module, a verification module and an output cache module. The control module is used to accept external configuration information and control the address pointer of the micro-instruction memory; the micro-instruction memory mainly records the configuration information of the system, control micro-instructions of various code rates and corresponding check matrix information, such as figure 2 As shown, the microinstruction memory is divided into a system configuration information area and a decoding microinstruction area; the system configuration information area has stored the starting address Add of the decoding microinstruction area of ​​different code rates and the correction factor Yita of different code rates ; The decoding ...

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Abstract

The invention relates to an LDPC code decoder supporting arbitrary various code rates, which comprises an input buffer module, a control module, an arithmetic processor module, an intermediate memory, a microinstruction memory, a switched network module, a verification module, an output buffer module and an Internet, and adopts a partially parallel structure. Based on a microinstruction control mode, the decoder stores different code rate information into the microinstruction memory to separate the code rates and a hardware structure, thereby realizing support for arbitrary various code rates without increasing hardware cost; the connecting wires of the decoder are in a neat order, so the complexity of the connecting wires is reduced greatly; and the decoder can effectively reduce the design period of a digital communication system and improve design efficiency.

Description

technical field [0001] The invention relates to an LDPC code decoder supporting arbitrary multiple code rates, which can be directly applied to the decoding of forward error correction channel codes, and belongs to the technical field of wireless digital communication. Background technique [0002] In modern digital communication systems, the design of error-correcting codes is an important part of ensuring reliable data transmission, because it can detect and correct errors introduced during signal transmission. Using Forward Error Correction Coding (FEC) can greatly improve transmission reliability. LDPC (LowDensity Parity Check) code is a forward error correction coding technology, also known as Gallager code. At present, LDPC codes have become a research hotspot in the field of channel coding, and have been widely used in wireless communication, satellite communication and other fields. LDPC code is a kind of linear block code, and the code word structure is determined...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
Inventor 英彦陈舟石泽文曾晓洋陈赟
Owner FUDAN UNIV
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