Multi-channel flash memory controller

Abstract

The invention relates to a multi-channel flash memory controller, which solves the defect of slow data read-write speed of a flash memory data in the prior art. The controller comprises an IDE interface module, a microprocessor and a flash memory management module which are connected with one another through two-port caches, wherein the flash memory management module comprises a flash memory interface command resolving unit, an inner management unit, a data interface management unit, a channel arbitration unit, a channel cache and a flash memory sequence unit; the data interface management unit, the channel arbitration unit and the flash memory sequence unit are sequentially connected; the data interface management unit and the channel arbitration unit are connected with the flash memory interface command resolving unit through the inner management unit; and a data transmission channel is independent of a command transmission channel. The multi-channel flash memory controller has the advantages of fast flash memory read-write speed, high data read-write reliability, high error correcting capacity, and long flash memory service life.

Description

technical field

[0001] The invention relates to a multi-channel flash memory controller. Background technique

[0002] As a new non-volatile storage medium, flash memory has become very popular in the field of consumer electronics due to its many advantages such as high storage density, easy portability, low power consumption, long data retention time after power failure, and good shock resistance. In the field of industry and military industry, it has also received more and more attention and popularity. In some large-capacity data storage applications, there are often multiple slices of flash memory cascaded or used as an entire column to expand storage space and improve data throughput. However, since the flash memory needs to wait for a long time after data is written, to ensure that the data is written correctly. Typically, a write needs to wait for 200us, and the maximum waiting time needs to be 700us. If you follow the normal operation idea and wait after writing d...

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