Method and apparatus for generating a floorplan using a reduced netlist

Abstract

One embodiment provides a system comprising methods and apparatuses that generate a floorplan for a hierarchical circuit design. More specifically, the system can receive a non-reduced netlist description for the hierarchical circuit design, and generate a reduced netlist which includes the interface logic elements of the netlist. The system can then generate the floorplan by using the reduced netlist as input. Note that the amount of computational resources and time required to generate a floorplan is substantially reduced because the system generates the floorplan using the reduced netlist instead of using the non-reduced netlist.

Description

technical field [0001] The present disclosure generally relates to electronic design automation. More specifically, the present disclosure relates to methods and apparatus for generating floorplans for circuit designs. Background technique [0002] Advances in semiconductor manufacturing technology have resulted in a significant increase in the number of transistors per semiconductor device. This increase in transistor count has enabled computer architecture to generate digital circuit designs of increasing complexity. As digital circuit designs become more complex, more effort is required in placing and routing circuit elements into transistor layouts. [0003] In a circuit design flow, a floorplan is typically generated for the circuit design before specific placement and routing is performed. The floorplan may specify how the various functional blocks in the circuit design are arranged on the chip. In addition, floorplanning is often used to guide the subsequent place...

AI Technical Summary

Problems solved by technology

[0005] For very large designs, a single floorplan iteration can take more than one business day

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