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Nonvolatile memory and method with index programming and reduced verify

A non-volatile, memory technology that is used in memory and programming operations to solve problems such as programming pulses increasing the number of cross-validations

Active Publication Date: 2011-05-18
SANDISK TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Additionally, the increase in programming pulses will increase the amount of cross-validation in conventional methods

Method used

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  • Nonvolatile memory and method with index programming and reduced verify
  • Nonvolatile memory and method with index programming and reduced verify
  • Nonvolatile memory and method with index programming and reduced verify

Examples

Experimental program
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Embodiment Construction

[0070] memory system

[0071] Figure 1 to Figure 10 An example memory system is illustrated in which various aspects of the invention may be implemented.

[0072] Figure 11 and Figure 12 Traditional programming techniques are illustrated.

[0073] Figure 13 to Figure 29 Various aspects and embodiments of the invention are illustrated.

[0074] figure 1 Functional blocks of a nonvolatile memory chip in which the present invention can be implemented are schematically illustrated. The memory chip 100 includes a two-dimensional array 200 of memory cells, a control circuit 210, and peripheral circuits such as decoders, read / write circuits, and multiplexers.

[0075] Memory array 200 is addressable by word lines via row decoder 230 (divided into 230A, 230B) and by bit lines via column decoder 260 (divided into 260A, 260B) (see also Figure 4 and 5). Read / write circuitry 270 (divided into 270A, 270B) allows a page of memory cells to be read or programmed in parallel. ...

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PUM

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Abstract

In a non-volatile memory, a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell is indexed during a first programming pass with the application of a series of incrementing programming pulses. The first programming pass is followed by verification and one or more subsequent programming passes to trim any short-falls to the respective target states. If a cell fails to verify to its target state, its program index is incremented and allows the cell to be programmed by the next pulse from the last received pulse. The verify and programming pass are repeated until all the cells in the group are verified to their respective target states. No verify operations between pulses are necessary.

Description

technical field [0001] The present invention relates generally to nonvolatile semiconductor memories such as Electrically Erasable Programmable Read Only Memory (EEPROM) and flash EEPROM, and in particular, to memories and programming in which the number of program-verify operations is minimized operate. Background technique [0002] Solid state memory capable of non-volatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as small form factor cards, has recently become the storage of choice in a variety of mobile and handheld devices, especially information appliances and consumer electronics. Unlike RAM (Random Access Memory), which is also solid-state memory, flash memory is non-volatile memory and retains its stored data even after power is cut off. Despite the higher cost, flash memory is being used more in mass storage applications. Traditional mass storage based on rotating magnetic media such as hard drives or floppy disks is not sui...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/56G11C16/10G11C16/34
CPCG11C16/0483G11C11/5628G11C2211/5621
Inventor 劳尔-阿德里安·瑟尼
Owner SANDISK TECH LLC
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