31results about How to "Improve programming accuracy" patented technology

Frequencies of viewing of first weekly broadcast programs by a user are detected in connection with past sections of the first weekly broadcast programs. At least one which has the detected viewing frequency greater than a predetermined threshold value is excluded from the first weekly broadcast programs to get second weekly broadcast programs. Program ranking measures representative of a relation between program attributes and user's preference are generated in response to (1) attributes of the past sections of the second weekly broadcast programs and (2) which of the past sections of the second weekly broadcast programs were viewed by the user. Future sections of the second weekly broadcast programs are ranked in response to (1) the generated program ranking measures and (2) attributes of the future sections of the second weekly broadcast programs.

Methods and apparatuses for controlling access to computer systems and for annotating media files. One embodiment includes a method including generating a challenge to a user, wherein the challenge includes a verify part and a read part. The methods also includes prompting the user to solve both the verify part of the challenge and the read part of the challenge; receiving input from the user; determining if the input from the user relative to the verify part of the challenge corresponds with the known answer for the verify part of the challenge; and identifying the input from the user relative to the read part of the challenge as an answer to the read part of the challenge, if the input from the user relative to the verify part of the challenge corresponds with the known answer for the verify part of the challenge.

In a non-volatile memory a group of memory cells is programmed respectively to their target states in parallel using a multiple-pass index programming method which reduces the number of verify steps. For each cell a program index is maintained storing the last programming voltage applied to the cell. Each cell is indexed during a first programming pass with the application of a series of incrementing programming pulses. The first programming pass is followed by verification and one or more subsequent programming passes to trim any short-falls to the respective target states. If a cell fails to verify to its target state, its program index is incremented and allows the cell to be programmed by the next pulse from the last received pulse. The verify and programming pass are repeated until all the cells in the group are verified to their respective target states. No verify operations between pulses are necessary.

A label printer applicator system programs labels having integrated circuits therein and applies the labels to a package. The applicator includes a tamp assembly having a tamp pad movement assembly and a tamp pad coupled thereto. An RF assembly, including an RF antenna, an RFID engine and antenna cable, is coupled to the tamp assembly. The tamp pad moves from a receiving position, where it receives a non-programmed label, to an extended position, where it applies the label to a package. The RFID engine provides RFID information to the RF antenna, which sends RFID information signals to the label to program the label. After the RFID label is applied to the package, the RF assembly sends test signals to the RFID label to determine whether the label has been properly programmed.

The invention discloses an OLED data driving circuit, an active TFT OLED panel based on the OLED data driving circuit and a driving method of the active TFT OLED panel based on the OLED data driving circuit. The current driving circuit is formed by the following parts including the current feed-forward part, the current feedback part, the comparison amplifier, the dynamic compensation part and the polarization power source. By means of the data driving circuit, current type TFT OLED pixels can be rapidly programmed with high accuracy. A gate driving line of the active TFT OLED panel based on the data driving circuit is two times that of a common panel, pixels in the direction of one gate driving line are divided into two different groups according to the parity of a dateline where the pixels are located, gate scanning time of two sets of pixels in the direction of the same line is respectively a half of the gate scanning time of the common panel, and two gate scanning lines are complemented and sequentially open the pixels in the direction of the same line.

A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to said gate terminal and a voltage value of said drain terminal is regulated so as to be maintained at a fixed value until a threshold voltage value of said memory cell is set at a desired threshold voltage level; and a disable phase that stops said programming and is triggered as soon as a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the attainment by the threshold voltage value of said memory cell of the desired threshold voltage value. A programming circuit is suitable for implementing this method.

A multiple pass programming scheme is optimized using capacitive coupling in the word line to word line direction during program-verify operations. A different pass voltage is used in different programming passes on an adjacent word line of a selected word line which is being verified. In particular, a lower pass voltage can be used in a first pass than in a second pass. The programming process may involve a word line look ahead or zigzag sequence in which WLn is programmed in a first pass, followed by WLn+1 in a first pass, followed by WLn in a second pass, followed by WLn+1 in a second pass. An initial programming pass may be performed before the first pass in which storage elements are programmed to an intermediate state and/or to a highest state.

Systems and methods are provided for program identification. For example, a first audio fingerprint corresponding to a first audio signal is acquired; whether one or more second audio fingerprints in a predetermined fingerprint database match with the first audio fingerprint is detected, a second audio fingerprint corresponding to a second audio signal; and in response to one of the second audio fingerprints matching with the first audio fingerprint, a program associated with the matching second audio signal is provided as a result for program identification associated with the first audio signal.

The invention discloses an FRU data burning method and system, equipment and a computer medium which are applied to a server. The method comprises the steps of: obtaining FRU data to be burnt; calculating the first check value of the FRU data to be burnt; and burning the FRU data to be burnt and the first check value to the target storage device, and setting the first check value to be readable inthe target storage device. In the present application, the method comprises the following steps: calculating the first check value of FRU data to be burnt; burning the FRU data to be burnt and the first check value to target storage device: setting the first verification value to be readable in the target storage device, so that the first verification value in the target storage device can be obtained no matter whether the FRU data to be burnt is in the standard format or not, the FRU data to be burnt which is burnt to the target storage device is verified through the first verification value, and the burning accuracy of the FRU data is improved. According to the FRU data burning system and device and the computer readable storage medium provided by the invention, the corresponding technical problems are also solved.

The invention provides a programming method for a multi-bit nonvolatile memory cell. The programming method comprises the steps of applying identical positive bias voltages on a substrate and a source terminal of a p-channel non-volatile memory cell, with a drain terminal grounded, applying a programming pulse voltage on a grid electrode; and programming the multi-bit nonvolatile memory cell in a setting state after a plurality of programming cycles comprising an electronic FN tunneling process and a channel hot electron injection process. Accordingly, the invention provides a programming method for a multi-bit nonvolatile memory unit array. A process for forming a memory cell threshold voltage steady state of the programming method provided by the invention is a self-convergence process and a repeated inspection process of a conventional programming method is omitted, so that programming speed of the multi-bit nonvolatile memory is effectively increased. By setting pulse parameters for the FN tunneling process and the channel hot electron injection process, the memory cell can be directly programmed to a designated state, so that programming accuracy of the multi-bit non-volatile memory cell is increased, and programming speed and accuracy can be taken into account at the same time.

A non-volatile memory device includes a first word line, a second word line, first memory cells, second memory cells, and an address decoder. The second word line is adjacent to the first word line. The first memory cells are connected to the first word line. The second memory cells are connected to the second word line. The second memory cells are connected to the first memory cells, respectively. The address decoder applies a first voltage to the first word line and applies a second voltage to the second word line in an over program period of the first memory cells. The first voltage is higher than a program voltage of the first and second memory cells. The second voltage is lower than a pass voltage of the first and second memory cells.

The invention discloses a burning device for chip processing, and belongs to the field of chip burning. The burning device for chip processing comprises a box body, a partition plate is arranged in the box body, a driving part is arranged at the top of the partition plate, a screw rod is connected to the output end of the driving part, burning assemblies are arranged below the partition plate, threaded sleeves are fixedly connected to the tops of the burning assemblies, and the threaded sleeves are in threaded connection with the screw rod; burning needles are arranged at the output ends of the burning assemblies, the burning needles are connected with the bottom wall of the box body in a sliding mode, and the multiple sets of burning assemblies are distributed in the box body at equal intervals; wherein the burning needles are connected with a pressing mechanism used for fixing a chip, the pressing mechanism comprises a fixing plate, a connecting rod and a cylinder body, the fixing plate is fixedly connected to the burning needles, the connecting rod is fixedly connected to the fixing plate, the positions of the connecting rod and the cylinder body can be changed, and an ash removal structure is arranged in the cylinder body; according to the invention, the groups of burning needles can be stretched out and drawn back, a chip is fixed when the burning needles are in contact with chip contacts, and a chip can be cleaned at the same time.