Method and system for active replication for Cache of multi-core processor

Abstract

The invention discloses a method and system for active replication for a Cache of a multi-core processor. The method comprises the following steps: S1, a host node analyzes the position and access times of a processor core which accesses to a data block in a shared L2 Cache, and selects a candidate replica node; S2, if the accessed times of the data block reach a replica threshold, the data block is replicated in the replica node and the position of a replica is recorded; S3, if receiving a read request for the replicated data block, the host node forwards the read request to the nearest replica node, and the replica node responds to the data block; S4, after receiving the response, a request node can record the position of the replica node in an address mapping table, and transmits a follow-up read request for the data block to the replica node. The method and the system avoid replica redundancy and unreasonable distribution caused by blind replication, and have the access delay which is close to the low delay of a private L2 Cache, and the capacity which is approximate to the large capacity of the shared L2 Cache.

Description

technical field [0001] The present invention relates to the technical field of Cache (cache memory), in particular to an active copy method and system for Cache of multi-core processors. Background technique [0002] The last level of Cache (L2 Cache) of a multi-core processor usually adopts a distributed design, which presents the characteristics of Non-Uniform Cache Access (NUCA). The access delay of the processor to the L2 Cache depends on the processor core and each Physical distance between L2 caches. There are two ways to organize L2 Cache: private L2 Cache design and shared L2 Cache design. The private L2 Cache design is that the processor core uses the local L2 Cache as a private Cache to obtain more local access and reduce access latency. The shared L2 Cache design distributes data to each L2 Cache through address crossing. There is a large amount of duplicate data in the private L2 Cache design, which reduces the effective capacity of the L2 Cache and leads to m...

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