Method and device for support vector conditional memory access

Abstract

Disclosed are a method and a device for supporting vector condition memory access. The method includes the steps that firstly, two programmable registers are set in a vector condition access unit (VCAC): an N-bit vector processing element (VPE) condition access register and an N-bit vector bank (VB) condition write back register; secondly, an instruction decoding unit receives a vector memory access instruction sent by an instruction distribution component to perform instruction decoding and decodes the memory access information in the instruction; thirdly, an address computing unit generates visiting requests (vrs) and addresses for visiting N VBs according to the memory access information and sends to the VCAU; fourthly, the VCAU subjects the all memory access information to conditional arrangement and data alignment; and fifthly the write back information of each VB access pipeline is input into a vector condition write back unit (VCWBU) for arrangement. The device comprises a vector memory (VM) which is composed of a memory access instruction decoding unit, the address computing unit, the VB, the VCAU and the VCWBU. According to the method and the device for supporting the vector condition memory access, the flexibility of memory access operation is improved, and the use ratio and memory access efficiency of the VM are effectively improved.

Description

technical field [0001] The present invention mainly relates to the design field of computer architecture, in particular to a vector data memory access control method and device in a vector processor for data-intensive applications such as wireless communication, which can better support multiple data streams by single instruction A variety of conditional access operations on vector memory (Vector Memory, VM) by vector processing elements (Vector Processing Elements, VPEs) operating in the stream (Single Instruction Multiple Data, SIMD) mode. Background technique [0002] With the development of computer technology and integrated circuit technology, the main frequency of microprocessors is getting higher and higher, and the increase in the computing power of the central processing unit (CPU) far exceeds the increase in memory performance. The "performance difference between CPU and memory" The "storage wall" problem has become a bottleneck restricting the further improvement ...

AI Technical Summary

Problems solved by technology

At present, the general vector memory access method has the following problems: (1) In order to realize the convenience and speed of memory access, only the memory access method of one-to-one correspondence between the vector processing unit and the vector memory bank in the vector memory is supported, that is, each VPE can only be accessed together It corresponds to the data in VB, and cannot access data in other VBs according to conditions; (2) VPE cannot access scalar data to vector processors, that is, it does not directly support multiple VPEs to read and write certain scalar data in vector processors Access operations, such data access can only be achieved by additional operations such as shuffling, packing, and unpacking between VPEs or by storing multiple copies of the same data in the memory, which will increase code density or reduce the storage space of the vector memory. The utilization rate reduces the efficiency and flexibility of the memory access device; (3) the general vector memory realizes the continuous access of bytes or halfwords and often needs to organize the memory with byte (8-bit) bit-wide storage banks, resulting in storage There are too many banks, and the organization and addressing of the memory banks are complicated, so the memory access state machine is more complicated

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