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Chip testing method and device thereof

A chip testing and chip technology, applied in the field of electronics, can solve the problems of increasing chip area and design cost

Active Publication Date: 2015-02-11
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The invention provides a chip testing method and device to solve the problem of increasing the chip area and design cost by adding additional pins on the chip for testing the chip

Method used

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  • Chip testing method and device thereof

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0054] Embodiment 1 of the present invention provides a chip testing method.

[0055] refer to figure 1 , shows a flow chart of a chip testing method in Embodiment 1 of the present invention.

[0056]Step 100, generating a scan mode signal after receiving a scan command; the scan mode signal puts the chip in a scan test mode or a working mode.

[0057] The scan command can be input through the original input pin of the chip, and the scan mode signal is generated inside the chip according to the scan command after receiving the scan command.

[0058] For different chips, the original input pins of the above-mentioned input scan command may have different choices, which may be determined according to the actual situation of the chip.

[0059] The above-mentioned scanning test mode is a mode for scanning and testing the chip; the above-mentioned working mode is a mode for the chip to work normally. The chip cannot be in the scanning test mode and the working mode at the same ti...

Embodiment 2

[0067] A chip testing method provided by an embodiment of the present invention is introduced in detail.

[0068] refer to figure 2 , shows a flow chart of a chip testing method in Embodiment 2 of the present invention.

[0069] Step 200, generating a scan mode signal after receiving a scan command; the scan mode signal puts the chip in a scan test mode.

[0070] Preferably, the above-mentioned scanning mode signal can make the chip be in two modes, which are:

[0071] (1) The scan mode signal makes the chip in the scan test mode:

[0072] When the scan mode signal is at a high level, the chip remains in the scan test mode or enters the scan test mode from the working mode.

[0073] If the current state of the chip is in the scan test mode and a high-level scan mode signal is generated at this time, the chip remains in the scan test mode.

[0074] If the current state of the chip is in the working mode, a high-level scan mode signal is generated at this time, and the chip...

Embodiment 3

[0107] A chip testing device provided by Embodiment 3 of the present invention is described in detail.

[0108] refer to Figure 4 , shows a structural diagram of a chip testing device in Embodiment 3 of the present invention.

[0109] Described a kind of chip testing device can comprise following module:

[0110] A scanning mode signal generating module 400 , a scanning required signal generating module 402 , and a chip testing module 404 .

[0111] The functions of each module and the relationship between each module are introduced in detail below.

[0112] The scan mode signal generating module 400 is configured to generate a scan mode signal after receiving a scan command; the scan mode signal makes the chip be in a scan test mode or a working mode.

[0113] The scanning required signal generating module 402 is configured to use the scanning mode signal and multiplex multiple original working pins of the chip to generate corresponding scanning required signals when the ...

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Abstract

The invention provides a chip testing method and a device thereof so as to solve the problems of chip area increase and design cost increase caused by additionally adding a pin on a chip in testing the chip. The method comprises a step of generating a scanning mode signal after receiving a scanning instruction, a step of allowing the chip to be in a scanning testing mode or a working mode by using the scanning mode signal, a step of generating a corresponding scanning needed signal by using the scanning mode signal and multiplexing a plurality of original working pins of the chip when the chip is in the scanning testing mode, and a step of using the scanning needed signal to carry out a chip testing operation. According to the method and the device thereof, on the basis of not increasing the chip pin, the plurality of original working pins of the chip are multiplexed to generate the scanning needed signal, all units in the chip are tested, the DFT requirement of the chip is satisfied, and thus the area and design cost of the chip are saved.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a chip testing method and device. Background technique [0002] In order to improve the quality and reliability of the chip, Design for Testability (DFT) is added to the digital part of the chip during the chip design process. DFT is to change the flip-flop in the sequential circuit into a flip-flop with a scan terminal, and then add some additional control logic to achieve the purpose of testability. Usually, DFT requires dedicated test pins, such as scan test mode (SCAN_MODE), scan enable (SCAN_EN), scan reset (SCAN_RST), scan serial input data (SCAN_DI), scan serial output data (SCAN_DO) and scan Serial clock (SCAN_CLK) and other 6 pins. [0003] If the above-mentioned 6 pins are additionally added on the chip for testing the chip, the area of ​​the chip will be increased, and a large chip design cost will also be brought. Especially for chips with few pins and small ar...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3185G01R31/3187
Inventor 薛子恒潘荣华
Owner GIGADEVICE SEMICON (BEIJING) INC