Deep packet inspection method and equipment and coprocessor

Abstract

Embodiments of the present invention provide a deep packet inspection method, a device, and a coprocessor. The deep packet inspection method comprises: a transceiver module of a coprocessor receiving an original data packet sent by a general processor, and sending the original data packet to a processor core of the coprocessor; the processor core calling a sub-coprocessor of the coprocessor to perform application layer parsing on the original data packet, so as to obtain an application layer parsing result; and the processor core sending the parsing result to the general processor, so that the general processor processes the original data packet according to the parsing result. The deep packet inspection method and apparatus provided in the embodiments of the present invention reduce occupancy of a resource of a general processor and improve the operating speed.

Description

technical field [0001] The embodiment of the present invention relates to computer technology, and in particular to a deep message detection method, device and coprocessor. Background technique [0002] Deep Packet Inspection (DPI) technology, as the core technology of network intrusion detection and application layer protocol identification, is playing an increasingly important role in the field of network and information security. DPI technology implements in-depth analysis of data packets through feature matching algorithms to obtain application information of data packets, thereby realizing services such as network optimization, application flow control, and security detection. [0003] In the prior art, the DPI service is usually implemented through a general-purpose processor, a matcher is integrated in the general-purpose processor, and the matcher is driven by software logic in the general-purpose processor to implement feature matching. Since general-purpose proces...

AI Technical Summary

Problems solved by technology

It can be seen that the logic is solidified through hardware, and the scalability is poor: when the DPI business logic (such as the three steps in the above example becomes four steps or the order is adjusted) changes, it is necessary to rewrite the hardware code, simulate and publish it to the live network device middle

It is difficult to quickly adapt to changes in network traffic; moreover, since the multiple steps of DPI business logic are respectively implemented by general-purpose processors in software and hardware acceleration chip logic, it is inevitable that there will be multiple interactions between general-purpose processors and hardware acceleration chips, resulting in DPI The processing delay is very large

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