Semiconductor device and test method
A semiconductor and conductive layer technology, applied in semiconductor/solid-state device testing/measurement, semiconductor devices, measurement devices, etc., can solve problems such as difficult to perform high-precision capacitance measurement
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[0120] Defects due to misalignment in the semiconductor process
[0121] In the manufacturing process of a semiconductor integrated circuit (IC) or the like, various test methods are used to detect whether the semiconductor IC is defective during the process or after the process (after the product is completed), thereby comparing the defective IC with the qualified IC Pick them out differently. In addition, in the case where a defect occurs, it is preferable to analyze in which step the defect occurred and the cause of the defect, and then provide feedback on the analysis result to the manufacturing process, thereby leading to an improvement in yield , or result in a reduction in the time necessary to improve yield.
[0122] Examples of defects created in such a process may include dislocations (overlap dislocations) between layers (between conductive layers). For example, when misalignment occurs during a wiring connection process between layers by means of vias, poor conne...
Deformed example 1-1
[0206] Figure 30A It is a schematic diagram illustrating an XY plane structure of a device group (device group 1B) according to Modification 1-1. Figure 30B is along Figure 30A A cross-sectional view taken on line II-II viewed in the direction of the arrow. In the device group 1A of the first embodiment described above, one (common) first conductive layer 11 is provided for the plurality of sub-conductive layers 12a; however, like the device group 1B in this modified example, a plurality of The first conductive layer 11. However, the plurality of first conductive layers 11 are electrically connected to each other. Like the first embodiment described above, the second conductive layer 12 includes a plurality of sub-conductive layers 12a, and in this example, the first conductive layer 11 and the sub-conductive layers 12a are arranged so that each sub-conductive layer 12a overlaps with its corresponding second conductive layer 12a. on a conductive layer 11.
[0207] In t...
Deformed example 1-2
[0209] Figure 31 It is a schematic diagram illustrating the XY plane structure of the device group (device group 1C) of Modification 1-2. In device group 1C of the present modification, a plurality of (here, two) first conductive layers 11 are provided, and second conductive layer 12 is arranged to straddle the two first conductive layers 11 . The first conductive layer 11 and the second conductive layer 12 are not necessarily arranged in a one-to-one manner, and it is only necessary that a plurality of sub-layers are arranged at relatively different positions with respect to the edges b1 and b2 of the first conductive layer 11. Conductive layer 12a.
[0210] Modification 1-3 and Modification 1-4
[0211] Figure 32 It is a schematic diagram illustrating the XY plane structure of the device group (device group 1D) of Modification 1-3. Figure 33 It is a schematic diagram illustrating the XY plane structure of the device group (device group 1E) of Modification 1-4. In the...
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