An Evaluation Method of Analog Circuit Layout Based on Uneven Grid

Abstract

The invention relates to an analog circuit wiring assessment method based on a non-uniform grid. The method is used for assessing a layout result of an analog circuit and guiding the layout optimization. The method comprises the steps that a non-uniform grid assessment graph is constructed; the possibility that all line grids pass all grid blocks of the grid assessment graph is assessed, and whether each grid block is congested or not is judged; according to a dynamic congestion degree drive wiring algorithm, the wiring path of starting points S of the line grids at the two ends and a target point T is estimated, whether the routability of the path can be achieved or not is judged according to the estimated fact about whether the wiring path grid blocks are congested or not, and therefore the routability rate is worked out. According to the method, the wiring path can be efficiently predicted, the routability is accurately assessed, and important significance is achieved for guiding layout optimization and elaborating the wiring process.

Description

technical field [0001] The invention relates to the evaluation of analog circuit wiring, in particular to an evaluation method for analog circuit wiring based on non-uniform grids. Background technique [0002] With the development of integrated circuits, the integration level of integrated circuits has been continuously improved, the feature size has become smaller and smaller, and the functions have become more and more diversified. In order to meet these requirements, various functional modules are concentrated on a chip, and a system on a chip (SoC) emerges as the times require. Analog circuit design automation and hybrid circuit design automation are becoming increasingly important in system-on-chip (SoC) design flows. Due to the complex constraints of analog circuits and the size constraints of chips, the automation process of analog circuit design is more complicated and difficult than that of digital circuit design. The analog circuit design automation process has ...

AI Technical Summary

Problems solved by technology

For analog circuits, the wiring net does not allow the net to walk on the device, and in the process of predicting possible wiring, many congestion evaluation algorithms only consider L and Z-type wiring paths, which cannot correctly reflect the actual circuit congestion. evaluation of

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