Multicast router based on package and circuit switching technology and working mode thereof

Abstract

The invention discloses a multicast router based on package and circuit switching technology and a working mode thereof. The multicast router based on package and circuit switching technology is characterized by being applied to a network on chip which includes a plurality of multicast routers, a plurality of resource nodes and a plurality of interconnection channels; each multicast router comprises an input state machine module, a priority encoder module, a decoder module, an address filtering module, an arbiter module, a crossbar module and an output state machine module; in a multicast data transmission event, a single requester node can simultaneously support sending the same batch of data to at most eight target nodes at the same time; and the success rate of establishing a link can be improved by the priority encoder module, and the target nodes are prevented from repeatedly routing by the address filtering module. The multicast router based on package and circuit switching technology can fully utilize the parallelism characteristic of the network on chip to save time consumed for the event of sending the same batch of data to the plurality of target nodes by the single requester node, and consumption on cache resources of the multicast routers in the network on chip is reduced.

Description

technical field [0001] The invention belongs to the technical field of on-chip network communication, in particular to the design of a multicast router based on "packet circuit" switching technology. Background technique [0002] With the continuous expansion of integrated circuit integration, the chip has gradually developed from a single function to a multi-functional system chip. Nowadays, a multifunctional system on chip (SoC, System on Chip) has been widely used. However, as the process feature size becomes smaller and smaller and the operating frequency rises rapidly, the shortcomings of the system-on-chip based on the bus architecture are gradually revealed. Mainly manifested in: [0003] (1) Poor scalability; [0004] (2) The resource utilization rate is low and cannot provide good parallel processing capability; [0005] (3) The power consumption and area caused by the global synchronization of a single clock greatly increase. [0006] In order to overcome the ...

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Problems solved by technology

[0003] (1) Poor scalability;

[0004] (2) The resource utilization rate is low and cannot provide good parallel processing capability;

[0005] (3) Significant increase in power consumption and area caused by global synchronization of a single clock

However, current research on "packet circuit" switching technology is limited to unicast communication functions

If the un...

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