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A method and device for realizing atomic operation based on the principle of cache consistency

A technology of atomic operation and implementation method, which is applied in the direction of multi-program device, program synchronization, etc., and can solve the problem of low efficiency of data synchronization operation

Active Publication Date: 2019-01-29
INSPUR BEIJING ELECTRONICS INFORMATION IND
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the system integrates a large number of processor cores and all initiate access to this address, the above operations may take a long time to complete, resulting in low efficiency of data synchronization operations

Method used

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  • A method and device for realizing atomic operation based on the principle of cache consistency
  • A method and device for realizing atomic operation based on the principle of cache consistency
  • A method and device for realizing atomic operation based on the principle of cache consistency

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Embodiment Construction

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0043] The embodiment of the present invention discloses an atomic operation realization method and device based on the principle of consistency, so as to reduce the read and write operation time involved in the atomic operation and improve data synchronization efficiency.

[0044] see figure 1 , a method for implementing an atomic operation based on the principle of cache consistency provided by an embodiment of the present invention includes:

[0045] S101. When...

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Abstract

The embodiment of the invention discloses an atomic operation implementation method and device based on the cache consistency principle. The method comprises the steps that when a processor executes an atomic operation for a locked address, an original protocol state of the locked address is converted into a maintaining state, wherein when the locked address is in the maintaining state, other processors are prevented from executing read-write operations on the locked address; the read-write operation of the processor for the locked address is executed, and when the locked address is in the maintaining state, a cache consistency maintaining mechanism of the processor ensures that the other processors need to pause and wait for executing the operation of the locked address only when the current processor can execute the read-write operation on the locked address, and therefore the atomic operation of the processor for the locked address is ensured.

Description

technical field [0001] The present invention relates to the technical field of computer system structure, and more specifically, relates to a method and device for implementing atomic operations based on the principle of cache consistency. Background technique [0002] In a multi-threaded program, the implementation of mutual exclusion access to shared variables generally depends on a spin lock (spinlock), and the implementation of a spin lock needs to perform a "test-set" atomic operation (TestAndSet). This atomic operation requires specialized hardware support to complete. In the implementation of the spin lock, the processor first performs a read operation on the locked address, and performs a test operation before writing to detect whether other processors have performed read or write operations on the address after the read operation is sent; if there is no other processing If the device performs read and write operations on the address, execute the write operation; ot...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/52
Inventor 倪璠
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
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