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Packaging structure and packaging method

A packaging structure and packaging method technology, applied in the field of semiconductors, can solve problems such as poor performance of image sensors, and achieve the effect of improving imaging quality

Active Publication Date: 2018-09-28
CHINA WAFER LEVEL CSP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The problem solved by the invention is that the performance of the image sensor formed by the prior art is poor

Method used

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  • Packaging structure and packaging method
  • Packaging structure and packaging method

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Experimental program
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Effect test

Embodiment Construction

[0026] It can be known from the background art that the performance of the image sensor formed by the prior art is not good.

[0027] The inventor of the present invention has conducted research on the process of packaging image sensor chips using wafer-level chip packaging technology in the prior art, and found that the poor performance of the image sensor formed by the prior art is due to the formation of The upper cover substrate above the sensing area will interfere with the light entering the sensing area and reduce the image quality.

[0028] Specifically, refer to figure 1 , figure 1 It shows a schematic diagram of a cross-sectional structure of an image sensor chip formed in the prior art. The image sensor chip includes: a substrate 10; a sensing area 20 located on the first surface of the substrate 10; bonding pads 21 located on the first surface of the substrate 10 on both sides of the sensing area 20; A second surface of the substrate 10 opposite to the first surface pe...

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Abstract

The invention provides a packaging structure and a packaging method. The packaging structure comprises a chip unit and an upper cover plate. A first surface of the chip unit contains an induction region. A first surface of the upper cover plate has a support structure; the upper cover covers the first surface of the chip unit; and the support structure is located between the upper cover plate and the chip unit. The induction region is arranged in a cavity encircled by the support structure and the first surface of the chip unit. The upper cover plate has a preset thickness, so that light reflected by the side wall of the upper cover plate can not irradiate the induction region directly. With the packaging structure and the packaging method, the interference light transmitted into the induction region can be reduced.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a packaging structure and a packaging method. Background technique [0002] Traditionally, the connection between the IC chip and the external circuit is achieved by wire bonding. As the feature size of IC chips shrinks and the scale of integrated circuits expands, wire bonding technology is no longer applicable. [0003] Wafer Level Chip Size Packaging (WLCSP) technology is a technology in which the entire wafer is packaged and tested and then cut to obtain a single finished chip. The packaged chip size is consistent with the bare chip. Wafer-level chip packaging technology has overturned traditional packaging such as ceramic leadless chip carriers (Ceramic Leadless Chip Carrier) and organic leadless chip carriers (Organic Leadless Chip Carrier). Short, thin and low price requirements. Chips packaged by wafer-level chip packaging technology have reached a high degree ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/146
Inventor 王之奇洪方圆
Owner CHINA WAFER LEVEL CSP