A bus virtualization method, device and system

Abstract

The invention discloses a method for bus virtualization. The method comprises: a root complex (RC) of a bus comprising a plurality of configuration register pairs, and each configuration register pair comprising an address register and a data register; the RC receiving a bus transaction message sent by a bus agent device in a processor core, the bus transaction message comprising an identification of a bus transaction this time, and from the plurality of configuration register pairs, the RC determining the configuration register pair that the processor core corresponding to the identification of the bus transaction this time should use. The method for the bus virtualization can ensure each process core can use an independent configuration register pair when the process core accesses a bus device, so as to ensure access correctness of the process core on the bus devices.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a bus virtualization method, device and system. Background technique [0002] The multi-core operating system in the prior art means that a physical computing node contains multiple processor cores, and the processor cores use the same global data bus, also called the front side bus, and the front side bus passes through the host bridge (host bridge) or root The transfer of the complex (RC, root complex) can be connected to the PCIE bus, so the kernel codes running on different processor cores can scan the bus devices connected to the PCIE bus through a configuration register pair, and check the bus devices on the PCI bus bus devices to access. A configuration register pair consists of an address register and a data register. [0003] In the prior art, each processor core can scan the bus and configure read-write bus devices through a pair of configuration registers. ...

AI Technical Summary

Problems solved by technology

In this way: all processor cores have only one configuration register pair, and multiple processor cores share the configuration register pair, so that the values ​​in the address register and data register will be confused, resulting in correctness problems

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